[llvm-commits] [llvm] r58883 - /llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
Evan Cheng
evan.cheng at apple.com
Fri Nov 7 17:44:14 PST 2008
Author: evancheng
Date: Fri Nov 7 19:44:13 2008
New Revision: 58883
URL: http://llvm.org/viewvc/llvm-project?rev=58883&view=rev
Log:
Skip over two-address use operands.
Modified:
llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=58883&r1=58882&r2=58883&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Fri Nov 7 19:44:13 2008
@@ -633,6 +633,8 @@
void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
unsigned ImplicitRd,
unsigned ImplicitRn) {
+ const TargetInstrDesc &TID = MI.getDesc();
+
// Part of binary is determined by TableGn.
unsigned Binary = getBinaryCodeForInstr(MI);
@@ -656,6 +658,10 @@
else
Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
+ // If this is a two-address operand, skip it. e.g. LDR_PRE.
+ if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
+ ++OpIdx;
+
const MachineOperand &MO2 = MI.getOperand(OpIdx);
unsigned AM2Opc = (ImplicitRn == ARM::PC)
? 0 : MI.getOperand(OpIdx+1).getImm();
@@ -689,6 +695,8 @@
void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
unsigned ImplicitRn) {
+ const TargetInstrDesc &TID = MI.getDesc();
+
// Part of binary is determined by TableGn.
unsigned Binary = getBinaryCodeForInstr(MI);
@@ -707,6 +715,10 @@
else
Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
+ // If this is a two-address operand, skip it. e.g. LDRH_POST.
+ if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
+ ++OpIdx;
+
const MachineOperand &MO2 = MI.getOperand(OpIdx);
unsigned AM3Opc = (ImplicitRn == ARM::PC)
? 0 : MI.getOperand(OpIdx+1).getImm();
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