[llvm-commits] [llvm] r58752 - in /llvm/trunk: lib/Target/X86/X86InstrMMX.td test/CodeGen/X86/mmx-vzmovl.ll

[Evan Cheng]

Author: evancheng
Date: Wed Nov  5 00:04:51 2008
New Revision: 58752

URL: http://llvm.org/viewvc/llvm-project?rev=58752&view=rev
Log:
Add more vector move low and zero-extend patterns.

Added:
    llvm/trunk/test/CodeGen/X86/mmx-vzmovl.ll
Modified:
    llvm/trunk/lib/Target/X86/X86InstrMMX.td

Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=58752&r1=58751&r2=58752&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Wed Nov  5 00:04:51 2008
@@ -585,6 +585,15 @@
            (MMX_MOVZDI2PDIrr GR32:$src)>; 
 }
 
+let AddedComplexity = 20 in {
+  def : Pat<(v8i8 (X86vzmovl (bc_v8i8 (load_mmx addr:$src)))),
+           (MMX_MOVZDI2PDIrm addr:$src)>; 
+  def : Pat<(v4i16 (X86vzmovl (bc_v4i16 (load_mmx addr:$src)))),
+           (MMX_MOVZDI2PDIrm addr:$src)>; 
+  def : Pat<(v2i32 (X86vzmovl (bc_v2i32 (load_mmx addr:$src)))),
+           (MMX_MOVZDI2PDIrm addr:$src)>; 
+}
+
 // Scalar to v4i16 / v8i8. The source may be a GR32, but only the lower
 // 8 or 16-bits matter.
 def : Pat<(bc_v8i8  (v2i32 (scalar_to_vector GR32:$src))),

Added: llvm/trunk/test/CodeGen/X86/mmx-vzmovl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mmx-vzmovl.ll?rev=58752&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/mmx-vzmovl.ll (added)
+++ llvm/trunk/test/CodeGen/X86/mmx-vzmovl.ll Wed Nov  5 00:04:51 2008
@@ -0,0 +1,15 @@
+; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep movd
+; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep movq
+
+define void @foo(<1 x i64>* %a, <1 x i64>* %b) nounwind {
+entry:
+	%0 = load <1 x i64>* %a, align 8		; <<1 x i64>> [#uses=1]
+	%1 = bitcast <1 x i64> %0 to <2 x i32>		; <<2 x i32>> [#uses=1]
+	%2 = and <2 x i32> %1, < i32 -1, i32 0 >		; <<2 x i32>> [#uses=1]
+	%3 = bitcast <2 x i32> %2 to <1 x i64>		; <<1 x i64>> [#uses=1]
+	store <1 x i64> %3, <1 x i64>* %b, align 8
+	br label %bb2
+
+bb2:		; preds = %entry
+	ret void
+}