[llvm-commits] [llvm] r58528 - /llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp

[Mon P Wang]

Author: wangmp
Date: Fri Oct 31 14:13:42 2008
New Revision: 58528

URL: http://llvm.org/viewvc/llvm-project?rev=58528&view=rev
Log:
x86_64 rip-relative and magic mode address

Modified:
    llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp

Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=58528&r1=58527&r2=58528&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Fri Oct 31 14:13:42 2008
@@ -338,7 +338,7 @@
   unsigned BaseReg = Base.getReg();
 
   // Is a SIB byte needed?
-  if (IndexReg.getReg() == 0 &&
+  if ((!Is64BitMode || DispForReloc) && IndexReg.getReg() == 0 &&
       (BaseReg == 0 || getX86RegNum(BaseReg) != N86::ESP)) {
     if (BaseReg == 0) {  // Just a displacement?
       // Emit special case [disp32] encoding
@@ -395,9 +395,13 @@
     if (BaseReg == 0) {
       // Handle the SIB byte for the case where there is no base.  The
       // displacement has already been output.
-      assert(IndexReg.getReg() && "Index register must be specified!");
-      emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5);
-    } else {
+      unsigned IndexRegNo;
+      if (IndexReg.getReg())
+        IndexRegNo = getX86RegNum(IndexReg.getReg());
+      else
+        IndexRegNo = 4;   // For example [ESP+1*<noreg>+4]
+      emitSIBByte(SS, IndexRegNo, 5);
+      } else {
       unsigned BaseRegNo = getX86RegNum(BaseReg);
       unsigned IndexRegNo;
       if (IndexReg.getReg())