[llvm-commits] [llvm] r58449 - /llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
Duncan Sands
baldrick at free.fr
Thu Oct 30 12:24:30 PDT 2008
Author: baldrick
Date: Thu Oct 30 14:24:28 2008
New Revision: 58449
URL: http://llvm.org/viewvc/llvm-project?rev=58449&view=rev
Log:
Shift amounts should have the type given by
getShiftAmountTy (i32 in the case of CellSPU).
Modified:
llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=58449&r1=58448&r2=58449&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Thu Oct 30 14:24:28 2008
@@ -2175,17 +2175,17 @@
? DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, N0)
: DAG.getConstant(cast<ConstantSDNode>(N0)->getZExtValue(),
MVT::i16));
- N1Opc = N1.getValueType().bitsLT(MVT::i16)
+ N1Opc = N1.getValueType().bitsLT(MVT::i32)
? ISD::ZERO_EXTEND
: ISD::TRUNCATE;
N1 = (N1.getOpcode() != ISD::Constant
- ? DAG.getNode(N1Opc, MVT::i16, N1)
+ ? DAG.getNode(N1Opc, MVT::i32, N1)
: DAG.getConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
- MVT::i16));
+ MVT::i32));
SDValue ExpandArg =
DAG.getNode(ISD::OR, MVT::i16, N0,
DAG.getNode(ISD::SHL, MVT::i16,
- N0, DAG.getConstant(8, MVT::i16)));
+ N0, DAG.getConstant(8, MVT::i32)));
return DAG.getNode(ISD::TRUNCATE, MVT::i8,
DAG.getNode(Opc, MVT::i16, ExpandArg, N1));
}
@@ -2526,7 +2526,7 @@
SDValue N = Op.getOperand(0);
SDValue Elt0 = DAG.getConstant(0, MVT::i16);
SDValue Mask0 = DAG.getConstant(0x0f, MVT::i16);
- SDValue Shift1 = DAG.getConstant(8, MVT::i16);
+ SDValue Shift1 = DAG.getConstant(8, MVT::i32);
SDValue Promote = DAG.getNode(SPUISD::PROMOTE_SCALAR, vecVT, N, N);
SDValue CNTB = DAG.getNode(SPUISD::CNTB, vecVT, Promote);
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