[llvm-commits] [llvm] r58230 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PreAllocSplitting.cpp lib/Target/X86/X86InstrInfo.cpp lib/Target/X86/X86InstrInfo.h lib/Target/X86/X86RegisterInfo.h test/CodeGen/X86/pre-split7.ll
Evan Cheng
evan.cheng at apple.com
Mon Oct 27 00:14:50 PDT 2008
Author: evancheng
Date: Mon Oct 27 02:14:50 2008
New Revision: 58230
URL: http://llvm.org/viewvc/llvm-project?rev=58230&view=rev
Log:
For now, don't split live intervals around x87 stack register barriers. FpGET_ST0_80 must be right after a call instruction (and ADJCALLSTACKUP) so we need to find a way to prevent reload of x87 registers between them.
Added:
llvm/trunk/test/CodeGen/X86/pre-split7.ll
Modified:
llvm/trunk/include/llvm/Target/TargetInstrInfo.h
llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/lib/Target/X86/X86InstrInfo.h
llvm/trunk/lib/Target/X86/X86RegisterInfo.h
Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=58230&r1=58229&r2=58230&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Mon Oct 27 02:14:50 2008
@@ -407,6 +407,13 @@
return false;
}
+ /// IgnoreRegisterClassBarriers - Returns true if pre-register allocation
+ /// live interval splitting pass should ignore barriers of the specified
+ /// register class.
+ virtual bool IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const{
+ return true;
+ }
+
/// getPointerRegClass - Returns a TargetRegisterClass used for pointer
/// values.
virtual const TargetRegisterClass *getPointerRegClass() const {
@@ -425,7 +432,6 @@
/// GetFunctionSizeInBytes - Returns the size of the specified MachineFunction.
///
virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0;
-
};
/// TargetInstrInfoImpl - This is the default implementation of
Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp?rev=58230&r1=58229&r2=58230&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp (original)
+++ llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Mon Oct 27 02:14:50 2008
@@ -659,6 +659,8 @@
// by the current barrier.
SmallVector<LiveInterval*, 8> Intervals;
for (const TargetRegisterClass **RC = RCs; *RC; ++RC) {
+ if (TII->IgnoreRegisterClassBarriers(*RC))
+ continue;
std::vector<unsigned> &VRs = MRI->getRegClassVirtRegs(*RC);
for (unsigned i = 0, e = VRs.size(); i != e; ++i) {
unsigned Reg = VRs[i];
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=58230&r1=58229&r2=58230&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Oct 27 02:14:50 2008
@@ -2411,6 +2411,14 @@
return false;
}
+bool X86InstrInfo::
+IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const {
+ // FIXME: Ignore bariers of x87 stack registers for now. We can't
+ // allow any loads of these registers before FpGet_ST0_80.
+ return RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
+ RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass;
+}
+
const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
if (Subtarget->is64Bit())
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=58230&r1=58229&r2=58230&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Mon Oct 27 02:14:50 2008
@@ -405,6 +405,11 @@
virtual
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
+ /// IgnoreRegisterClassBarriers - Returns true if pre-register allocation
+ /// live interval splitting pass should ignore barriers of the specified
+ /// register class.
+ bool IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const;
+
const TargetRegisterClass *getPointerRegClass() const;
// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.h?rev=58230&r1=58229&r2=58230&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.h Mon Oct 27 02:14:50 2008
@@ -94,6 +94,10 @@
/// Code Generation virtual methods...
///
+
+ /// getCrossCopyRegClass - Returns a legal register class to copy a register
+ /// in the specified class to or from. Returns NULL if it is possible to copy
+ /// between a two registers of the specified class.
const TargetRegisterClass *
getCrossCopyRegClass(const TargetRegisterClass *RC) const;
Added: llvm/trunk/test/CodeGen/X86/pre-split7.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pre-split7.ll?rev=58230&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pre-split7.ll (added)
+++ llvm/trunk/test/CodeGen/X86/pre-split7.ll Mon Oct 27 02:14:50 2008
@@ -0,0 +1,34 @@
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -pre-alloc-split
+
+ at object_distance = external global double, align 8 ; <double*> [#uses=1]
+ at axis_slope_angle = external global double, align 8 ; <double*> [#uses=1]
+ at current_surfaces.b = external global i1 ; <i1*> [#uses=1]
+
+declare double @sin(double) nounwind readonly
+
+declare double @asin(double) nounwind readonly
+
+declare double @tan(double) nounwind readonly
+
+define fastcc void @trace_line(i32 %line) nounwind {
+entry:
+ %.b3 = load i1* @current_surfaces.b ; <i1> [#uses=1]
+ br i1 %.b3, label %bb, label %return
+
+bb: ; preds = %bb, %entry
+ %0 = tail call double @asin(double 0.000000e+00) nounwind readonly ; <double> [#uses=1]
+ %1 = add double 0.000000e+00, %0 ; <double> [#uses=2]
+ %2 = tail call double @asin(double 0.000000e+00) nounwind readonly ; <double> [#uses=1]
+ %3 = sub double %1, %2 ; <double> [#uses=2]
+ store double %3, double* @axis_slope_angle, align 8
+ %4 = fdiv double %1, 2.000000e+00 ; <double> [#uses=1]
+ %5 = tail call double @sin(double %4) nounwind readonly ; <double> [#uses=1]
+ %6 = mul double 0.000000e+00, %5 ; <double> [#uses=1]
+ %7 = tail call double @tan(double %3) nounwind readonly ; <double> [#uses=0]
+ %8 = add double 0.000000e+00, %6 ; <double> [#uses=1]
+ store double %8, double* @object_distance, align 8
+ br label %bb
+
+return: ; preds = %entry
+ ret void
+}
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