[llvm-commits] vector widening patch

[Stefanus Du Toit]

Hi Mon Ping,

On 20-Oct-08, at 1:46 PM, Mon Ping Wang wrote:
> No numbers to back that choice up.  The thinking was that instead of
> worrying about packing and unpacking a two element vector that it
> might be cheaper to treat it as two scalar computation as a general
> rule.  For x86 with SSE2+, I have no problem saying that we should
> always widen.  With MMX, it is less clear.  Do you think that in
> general, it always make sense to widen?

It probably depends on your architecture. In our experience, using MMX  
when you have SSE2 is not productive, and so we actually just turn off  
anything that legalizes MMX operations and types. The one  
microarchitecture where you might benefit from MMX is pre-Barcelona  
Opteron, which supports SSE2 but performs and SSE operation as two 64  
bit operations. But in this case, 2-vectors would be legal anyways.

I would think that for most ISAs, if a 2-vector is not legal, it  
probably makes sense to widen. Chances are the two scalars are already  
sitting in a vector register, and thus scalarizing will actually  
involve more packing and unpacking. A client could always scalarize in  
the frontend (which is much easier than widening in the frontend!) if  
they really want to -- if they're using 2-vectors, that's probably a  
good indication they want their data in vector registers (I know  
that's the case for us). [*]

But others might have different experiences. Please speak up!

--
Stefanus Du Toit <stefanus.dutoit at rapidmind.com>
   RapidMind Inc.
   phone: +1 519 885 5455 x116 -- fax: +1 519 885 1463

[*] We have seen cases where scalarizing is a benefit, but in those  
cases the values where typically being packed in the IR (rather than  
loaded as a vector), and usually related to induction variables in  
loops, where scalarizing can enable other optimizations. I would be  
interested in an optimization pass that recognized such cases and  
scalarized them, but this would have to happen at the IR level.