[llvm-commits] [llvm] r57700 - in /llvm/branches/release_24: lib/CodeGen/SelectionDAG/ lib/Target/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/IA64/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ test/CodeGen/X86/
Tanya Lattner
tonic at nondot.org
Fri Oct 17 10:53:06 PDT 2008
Author: tbrethou
Date: Fri Oct 17 12:53:06 2008
New Revision: 57700
URL: http://llvm.org/viewvc/llvm-project?rev=57700&view=rev
Log:
Merge from mainline.
Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as
parameters instead of raw Constants. This prevents the constants from
being selected by the isel pass, fixing PR2735.
Added:
llvm/branches/release_24/test/CodeGen/X86/2008-10-11-CallCrash.ll
- copied unchanged from r57385, llvm/trunk/test/CodeGen/X86/2008-10-11-CallCrash.ll
Modified:
llvm/branches/release_24/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/branches/release_24/lib/Target/ARM/ARMISelLowering.cpp
llvm/branches/release_24/lib/Target/ARM/ARMInstrInfo.td
llvm/branches/release_24/lib/Target/Alpha/AlphaISelLowering.cpp
llvm/branches/release_24/lib/Target/Alpha/AlphaInstrInfo.td
llvm/branches/release_24/lib/Target/CellSPU/SPUISelLowering.cpp
llvm/branches/release_24/lib/Target/CellSPU/SPUInstrInfo.td
llvm/branches/release_24/lib/Target/IA64/IA64ISelLowering.cpp
llvm/branches/release_24/lib/Target/Mips/MipsISelLowering.cpp
llvm/branches/release_24/lib/Target/Mips/MipsInstrInfo.td
llvm/branches/release_24/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/branches/release_24/lib/Target/PowerPC/PPCInstrInfo.td
llvm/branches/release_24/lib/Target/Sparc/SparcISelLowering.cpp
llvm/branches/release_24/lib/Target/Sparc/SparcInstrInfo.td
llvm/branches/release_24/lib/Target/TargetSelectionDAG.td
llvm/branches/release_24/lib/Target/X86/X86ISelLowering.cpp
llvm/branches/release_24/lib/Target/X86/X86Instr64bit.td
llvm/branches/release_24/lib/Target/X86/X86InstrInfo.td
Modified: llvm/branches/release_24/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_24/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=57700&r1=57699&r2=57700&view=diff
==============================================================================
--- llvm/branches/release_24/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/branches/release_24/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Oct 17 12:53:06 2008
@@ -1678,8 +1678,7 @@
// Chain the dynamic stack allocation so that it doesn't modify the stack
// pointer when other instructions are using the stack.
- Chain = DAG.getCALLSEQ_START(Chain,
- DAG.getConstant(0, TLI.getPointerTy()));
+ Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
SDValue Size = Tmp2.getOperand(1);
SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT);
@@ -1693,11 +1692,8 @@
Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
- Tmp2 =
- DAG.getCALLSEQ_END(Chain,
- DAG.getConstant(0, TLI.getPointerTy()),
- DAG.getConstant(0, TLI.getPointerTy()),
- SDValue());
+ Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
+ DAG.getIntPtrConstant(0, true), SDValue());
Tmp1 = LegalizeOp(Tmp1);
Tmp2 = LegalizeOp(Tmp2);
Modified: llvm/branches/release_24/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_24/lib/Target/ARM/ARMISelLowering.cpp?rev=57700&r1=57699&r2=57700&view=diff
==============================================================================
--- llvm/branches/release_24/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/release_24/lib/Target/ARM/ARMISelLowering.cpp Fri Oct 17 12:53:06 2008
@@ -430,8 +430,7 @@
// Adjust the stack pointer for the new arguments...
// These operations are automatically eliminated by the prolog/epilog pass
- Chain = DAG.getCALLSEQ_START(Chain,
- DAG.getConstant(NumBytes, MVT::i32));
+ Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
@@ -603,10 +602,8 @@
&Ops[0], Ops.size());
InFlag = Chain.getValue(1);
- Chain = DAG.getCALLSEQ_END(Chain,
- DAG.getConstant(NumBytes, MVT::i32),
- DAG.getConstant(0, MVT::i32),
- InFlag);
+ Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
+ DAG.getIntPtrConstant(0, true), InFlag);
if (RetVT != MVT::Other)
InFlag = Chain.getValue(1);
Modified: llvm/branches/release_24/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_24/lib/Target/ARM/ARMInstrInfo.td?rev=57700&r1=57699&r2=57700&view=diff
==============================================================================
--- llvm/branches/release_24/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/branches/release_24/lib/Target/ARM/ARMInstrInfo.td Fri Oct 17 12:53:06 2008
@@ -452,12 +452,12 @@
def ADJCALLSTACKUP :
PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p),
"@ ADJCALLSTACKUP $amt1",
- [(ARMcallseq_end imm:$amt1, imm:$amt2)]>;
+ [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
def ADJCALLSTACKDOWN :
PseudoInst<(outs), (ins i32imm:$amt, pred:$p),
"@ ADJCALLSTACKDOWN $amt",
- [(ARMcallseq_start imm:$amt)]>;
+ [(ARMcallseq_start timm:$amt)]>;
}
def DWARF_LOC :
Modified: llvm/branches/release_24/lib/Target/Alpha/AlphaISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_24/lib/Target/Alpha/AlphaISelLowering.cpp?rev=57700&r1=57699&r2=57700&view=diff
==============================================================================
--- llvm/branches/release_24/lib/Target/Alpha/AlphaISelLowering.cpp (original)
+++ llvm/branches/release_24/lib/Target/Alpha/AlphaISelLowering.cpp Fri Oct 17 12:53:06 2008
@@ -358,8 +358,7 @@
if (Args.size() > 6)
NumBytes = (Args.size() - 6) * 8;
- Chain = DAG.getCALLSEQ_START(Chain,
- DAG.getConstant(NumBytes, getPointerTy()));
+ Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
std::vector<SDValue> args_to_use;
for (unsigned i = 0, e = Args.size(); i != e; ++i)
{
@@ -402,10 +401,8 @@
Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
SDValue TheCall = DAG.getNode(AlphaISD::CALL, RetVals, &Ops[0], Ops.size());
Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
- Chain = DAG.getCALLSEQ_END(Chain,
- DAG.getConstant(NumBytes, getPointerTy()),
- DAG.getConstant(0, getPointerTy()),
- SDValue());
+ Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
+ DAG.getIntPtrConstant(0, true), SDValue());
SDValue RetVal = TheCall;
if (RetTyVT != ActualRetTyVT) {
Modified: llvm/branches/release_24/lib/Target/Alpha/AlphaInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_24/lib/Target/Alpha/AlphaInstrInfo.td?rev=57700&r1=57699&r2=57700&view=diff
==============================================================================
--- llvm/branches/release_24/lib/Target/Alpha/AlphaInstrInfo.td (original)
+++ llvm/branches/release_24/lib/Target/Alpha/AlphaInstrInfo.td Fri Oct 17 12:53:06 2008
@@ -151,10 +151,10 @@
let hasCtrlDep = 1, Defs = [R30], Uses = [R30] in {
def ADJUSTSTACKUP : PseudoInstAlpha<(outs), (ins s64imm:$amt),
"; ADJUP $amt",
- [(callseq_start imm:$amt)], s_pseudo>;
+ [(callseq_start timm:$amt)], s_pseudo>;
def ADJUSTSTACKDOWN : PseudoInstAlpha<(outs), (ins s64imm:$amt1, s64imm:$amt2),
"; ADJDOWN $amt1",
- [(callseq_end imm:$amt1, imm:$amt2)], s_pseudo>;
+ [(callseq_end timm:$amt1, timm:$amt2)], s_pseudo>;
}
def ALTENT : PseudoInstAlpha<(outs), (ins s64imm:$TARGET), "$$$TARGET..ng:\n", [], s_pseudo>;
Modified: llvm/branches/release_24/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_24/lib/Target/CellSPU/SPUISelLowering.cpp?rev=57700&r1=57699&r2=57700&view=diff
==============================================================================
--- llvm/branches/release_24/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/branches/release_24/lib/Target/CellSPU/SPUISelLowering.cpp Fri Oct 17 12:53:06 2008
@@ -1171,7 +1171,8 @@
// Update number of stack bytes actually used, insert a call sequence start
NumStackBytes = (ArgOffset - SPUFrameInfo::minStackSize());
- Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumStackBytes, PtrVT));
+ Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumStackBytes,
+ true));
if (!MemOpChains.empty()) {
// Adjust the stack pointer for the stack arguments.
@@ -1243,10 +1244,8 @@
&Ops[0], Ops.size());
InFlag = Chain.getValue(1);
- Chain = DAG.getCALLSEQ_END(Chain,
- DAG.getConstant(NumStackBytes, PtrVT),
- DAG.getConstant(0, PtrVT),
- InFlag);
+ Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumStackBytes, true),
+ DAG.getIntPtrConstant(0, true), InFlag);
if (TheCall->getValueType(0) != MVT::Other)
InFlag = Chain.getValue(1);
Modified: llvm/branches/release_24/lib/Target/CellSPU/SPUInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_24/lib/Target/CellSPU/SPUInstrInfo.td?rev=57700&r1=57699&r2=57700&view=diff
==============================================================================
--- llvm/branches/release_24/lib/Target/CellSPU/SPUInstrInfo.td (original)
+++ llvm/branches/release_24/lib/Target/CellSPU/SPUInstrInfo.td Fri Oct 17 12:53:06 2008
@@ -24,10 +24,10 @@
let hasCtrlDep = 1, Defs = [R1], Uses = [R1] in {
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm_i32:$amt),
"${:comment} ADJCALLSTACKDOWN",
- [(callseq_start imm:$amt)]>;
+ [(callseq_start timm:$amt)]>;
def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm_i32:$amt),
"${:comment} ADJCALLSTACKUP",
- [(callseq_end imm:$amt)]>;
+ [(callseq_end timm:$amt)]>;
}
//===----------------------------------------------------------------------===//
Modified: llvm/branches/release_24/lib/Target/IA64/IA64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_24/lib/Target/IA64/IA64ISelLowering.cpp?rev=57700&r1=57699&r2=57700&view=diff
==============================================================================
--- llvm/branches/release_24/lib/Target/IA64/IA64ISelLowering.cpp (original)
+++ llvm/branches/release_24/lib/Target/IA64/IA64ISelLowering.cpp Fri Oct 17 12:53:06 2008
@@ -333,7 +333,7 @@
// "stack frame not 16-byte aligned!");
NumBytes = (NumBytes+15) & ~15;
- Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
+ Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
SDValue StackPtr;
std::vector<SDValue> Stores;
@@ -543,10 +543,8 @@
}
}
- Chain = DAG.getCALLSEQ_END(Chain,
- DAG.getConstant(NumBytes, getPointerTy()),
- DAG.getConstant(0, getPointerTy()),
- SDValue());
+ Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
+ DAG.getIntPtrConstant(0, true), SDValue());
return std::make_pair(RetVal, Chain);
}
Modified: llvm/branches/release_24/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_24/lib/Target/Mips/MipsISelLowering.cpp?rev=57700&r1=57699&r2=57700&view=diff
==============================================================================
--- llvm/branches/release_24/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/branches/release_24/lib/Target/Mips/MipsISelLowering.cpp Fri Oct 17 12:53:06 2008
@@ -608,8 +608,7 @@
// Get a count of how many bytes are to be pushed on the stack.
unsigned NumBytes = CCInfo.getNextStackOffset();
- Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
- getPointerTy()));
+ Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
// With EABI is it possible to have 16 args on registers.
SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
@@ -715,10 +714,8 @@
InFlag = Chain.getValue(1);
// Create the CALLSEQ_END node.
- Chain = DAG.getCALLSEQ_END(Chain,
- DAG.getConstant(NumBytes, getPointerTy()),
- DAG.getConstant(0, getPointerTy()),
- InFlag);
+ Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
+ DAG.getIntPtrConstant(0, true), InFlag);
InFlag = Chain.getValue(1);
// Create a stack location to hold GP when PIC is used. This stack
Modified: llvm/branches/release_24/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_24/lib/Target/Mips/MipsInstrInfo.td?rev=57700&r1=57699&r2=57700&view=diff
==============================================================================
--- llvm/branches/release_24/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/branches/release_24/lib/Target/Mips/MipsInstrInfo.td Fri Oct 17 12:53:06 2008
@@ -393,10 +393,10 @@
let Defs = [SP], Uses = [SP] in {
def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
"!ADJCALLSTACKDOWN $amt",
- [(callseq_start imm:$amt)]>;
+ [(callseq_start timm:$amt)]>;
def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
"!ADJCALLSTACKUP $amt1",
- [(callseq_end imm:$amt1, imm:$amt2)]>;
+ [(callseq_end timm:$amt1, timm:$amt2)]>;
}
// Some assembly macros need to avoid pseudoinstructions and assembler
Modified: llvm/branches/release_24/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_24/lib/Target/PowerPC/PPCISelLowering.cpp?rev=57700&r1=57699&r2=57700&view=diff
==============================================================================
--- llvm/branches/release_24/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/branches/release_24/lib/Target/PowerPC/PPCISelLowering.cpp Fri Oct 17 12:53:06 2008
@@ -2142,8 +2142,7 @@
// Adjust the stack pointer for the new arguments...
// These operations are automatically eliminated by the prolog/epilog pass
- Chain = DAG.getCALLSEQ_START(Chain,
- DAG.getConstant(NumBytes, PtrVT));
+ Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
SDValue CallSeqStart = Chain;
// Load the return address and frame pointer so it can be move somewhere else
@@ -2476,8 +2475,8 @@
SmallVector<SDValue, 8> CallSeqOps;
SDVTList CallSeqNodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
CallSeqOps.push_back(Chain);
- CallSeqOps.push_back(DAG.getIntPtrConstant(NumBytes));
- CallSeqOps.push_back(DAG.getIntPtrConstant(0));
+ CallSeqOps.push_back(DAG.getIntPtrConstant(NumBytes, true));
+ CallSeqOps.push_back(DAG.getIntPtrConstant(0, true));
if (InFlag.getNode())
CallSeqOps.push_back(InFlag);
Chain = DAG.getNode(ISD::CALLSEQ_END, CallSeqNodeTys, &CallSeqOps[0],
@@ -2564,9 +2563,8 @@
Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
InFlag = Chain.getValue(1);
- Chain = DAG.getCALLSEQ_END(Chain,
- DAG.getConstant(NumBytes, PtrVT),
- DAG.getConstant(BytesCalleePops, PtrVT),
+ Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
+ DAG.getIntPtrConstant(BytesCalleePops, true),
InFlag);
if (TheCall->getValueType(0) != MVT::Other)
InFlag = Chain.getValue(1);
Modified: llvm/branches/release_24/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_24/lib/Target/PowerPC/PPCInstrInfo.td?rev=57700&r1=57699&r2=57700&view=diff
==============================================================================
--- llvm/branches/release_24/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/branches/release_24/lib/Target/PowerPC/PPCInstrInfo.td Fri Oct 17 12:53:06 2008
@@ -342,10 +342,10 @@
let Defs = [R1], Uses = [R1] in {
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt),
"${:comment} ADJCALLSTACKDOWN",
- [(callseq_start imm:$amt)]>;
+ [(callseq_start timm:$amt)]>;
def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2),
"${:comment} ADJCALLSTACKUP",
- [(callseq_end imm:$amt1, imm:$amt2)]>;
+ [(callseq_end timm:$amt1, timm:$amt2)]>;
}
def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
Modified: llvm/branches/release_24/lib/Target/Sparc/SparcISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_24/lib/Target/Sparc/SparcISelLowering.cpp?rev=57700&r1=57699&r2=57700&view=diff
==============================================================================
--- llvm/branches/release_24/lib/Target/Sparc/SparcISelLowering.cpp (original)
+++ llvm/branches/release_24/lib/Target/Sparc/SparcISelLowering.cpp Fri Oct 17 12:53:06 2008
@@ -269,7 +269,7 @@
// Keep stack frames 8-byte aligned.
ArgsSize = (ArgsSize+7) & ~7;
- Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize));
+ Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true));
SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
SmallVector<SDValue, 8> MemOpChains;
@@ -420,9 +420,8 @@
Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.getNode() ? 3 : 2);
InFlag = Chain.getValue(1);
- Chain = DAG.getCALLSEQ_END(Chain,
- DAG.getConstant(ArgsSize, MVT::i32),
- DAG.getConstant(0, MVT::i32), InFlag);
+ Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
+ DAG.getIntPtrConstant(0, true), InFlag);
InFlag = Chain.getValue(1);
// Assign locations to each value returned by this call.
Modified: llvm/branches/release_24/lib/Target/Sparc/SparcInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_24/lib/Target/Sparc/SparcInstrInfo.td?rev=57700&r1=57699&r2=57700&view=diff
==============================================================================
--- llvm/branches/release_24/lib/Target/Sparc/SparcInstrInfo.td (original)
+++ llvm/branches/release_24/lib/Target/Sparc/SparcInstrInfo.td Fri Oct 17 12:53:06 2008
@@ -210,10 +210,10 @@
let Defs = [O6], Uses = [O6] in {
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
"!ADJCALLSTACKDOWN $amt",
- [(callseq_start imm:$amt)]>;
+ [(callseq_start timm:$amt)]>;
def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
"!ADJCALLSTACKUP $amt1",
- [(callseq_end imm:$amt1, imm:$amt2)]>;
+ [(callseq_end timm:$amt1, timm:$amt2)]>;
}
// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
Modified: llvm/branches/release_24/lib/Target/TargetSelectionDAG.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_24/lib/Target/TargetSelectionDAG.td?rev=57700&r1=57699&r2=57700&view=diff
==============================================================================
--- llvm/branches/release_24/lib/Target/TargetSelectionDAG.td (original)
+++ llvm/branches/release_24/lib/Target/TargetSelectionDAG.td Fri Oct 17 12:53:06 2008
@@ -240,6 +240,7 @@
def srcvalue;
def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
+def timm : SDNode<"ISD::TargetConstant", SDTIntLeaf , [], "ConstantSDNode">;
def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
Modified: llvm/branches/release_24/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_24/lib/Target/X86/X86ISelLowering.cpp?rev=57700&r1=57699&r2=57700&view=diff
==============================================================================
--- llvm/branches/release_24/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/release_24/lib/Target/X86/X86ISelLowering.cpp Fri Oct 17 12:53:06 2008
@@ -1498,7 +1498,7 @@
MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
}
- Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes));
+ Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
SDValue RetAddrFrIdx;
// Load return adress for tail calls.
@@ -1714,8 +1714,8 @@
if (IsTailCall) {
Ops.push_back(Chain);
- Ops.push_back(DAG.getIntPtrConstant(NumBytes));
- Ops.push_back(DAG.getIntPtrConstant(0));
+ Ops.push_back(DAG.getIntPtrConstant(NumBytes, true));
+ Ops.push_back(DAG.getIntPtrConstant(0, true));
if (InFlag.getNode())
Ops.push_back(InFlag);
Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
@@ -1777,8 +1777,9 @@
// Returns a flag for retval copy to use.
Chain = DAG.getCALLSEQ_END(Chain,
- DAG.getIntPtrConstant(NumBytes),
- DAG.getIntPtrConstant(NumBytesForCalleeToPush),
+ DAG.getIntPtrConstant(NumBytes, true),
+ DAG.getIntPtrConstant(NumBytesForCalleeToPush,
+ true),
InFlag);
InFlag = Chain.getValue(1);
@@ -5112,7 +5113,7 @@
MVT IntPtr = getPointerTy();
MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
- Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0));
+ Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
Flag = Chain.getValue(1);
@@ -5127,8 +5128,8 @@
Flag = Chain.getValue(1);
Chain = DAG.getCALLSEQ_END(Chain,
- DAG.getIntPtrConstant(0),
- DAG.getIntPtrConstant(0),
+ DAG.getIntPtrConstant(0, true),
+ DAG.getIntPtrConstant(0, true),
Flag);
Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1);
Modified: llvm/branches/release_24/lib/Target/X86/X86Instr64bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_24/lib/Target/X86/X86Instr64bit.td?rev=57700&r1=57699&r2=57700&view=diff
==============================================================================
--- llvm/branches/release_24/lib/Target/X86/X86Instr64bit.td (original)
+++ llvm/branches/release_24/lib/Target/X86/X86Instr64bit.td Fri Oct 17 12:53:06 2008
@@ -94,11 +94,11 @@
let Defs = [RSP, EFLAGS], Uses = [RSP] in {
def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
"#ADJCALLSTACKDOWN",
- [(X86callseq_start imm:$amt)]>,
+ [(X86callseq_start timm:$amt)]>,
Requires<[In64BitMode]>;
def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
"#ADJCALLSTACKUP",
- [(X86callseq_end imm:$amt1, imm:$amt2)]>,
+ [(X86callseq_end timm:$amt1, timm:$amt2)]>,
Requires<[In64BitMode]>;
}
Modified: llvm/branches/release_24/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_24/lib/Target/X86/X86InstrInfo.td?rev=57700&r1=57699&r2=57700&view=diff
==============================================================================
--- llvm/branches/release_24/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/branches/release_24/lib/Target/X86/X86InstrInfo.td Fri Oct 17 12:53:06 2008
@@ -345,11 +345,11 @@
let Defs = [ESP, EFLAGS], Uses = [ESP] in {
def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
"#ADJCALLSTACKDOWN",
- [(X86callseq_start imm:$amt)]>,
+ [(X86callseq_start timm:$amt)]>,
Requires<[In32BitMode]>;
def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
"#ADJCALLSTACKUP",
- [(X86callseq_end imm:$amt1, imm:$amt2)]>,
+ [(X86callseq_end timm:$amt1, timm:$amt2)]>,
Requires<[In32BitMode]>;
}
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