[llvm-commits] [llvm] r57686 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp lib/CodeGen/SelectionDAG/TargetLowering.cpp
Chris Lattner
sabre at nondot.org
Fri Oct 17 09:21:11 PDT 2008
Author: lattner
Date: Fri Oct 17 11:21:11 2008
New Revision: 57686
URL: http://llvm.org/viewvc/llvm-project?rev=57686&view=rev
Log:
add an assert so that PR2356 explodes instead of running off an
array. Improve some minor comments, refactor some helpers in
AsmOperandInfo. No functionality change for valid code.
Modified:
llvm/trunk/include/llvm/Target/TargetLowering.h
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=57686&r1=57685&r2=57686&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Fri Oct 17 11:21:11 2008
@@ -1181,6 +1181,8 @@
/// lowering.
struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
/// ConstraintCode - This contains the actual string for the code, like "m".
+ /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
+ /// most closely matches the operand.
std::string ConstraintCode;
/// ConstraintType - Information about the constraint code, e.g. Register,
@@ -1194,6 +1196,14 @@
/// ConstraintVT - The ValueType for the operand value.
MVT ConstraintVT;
+
+ /// isMatchingConstraint - Return true of this is an input operand that is a
+ /// matching constraint like "4".
+ bool isMatchingConstraint() const;
+
+ /// getMatchedOperand - If this is an input matching constraint, this method
+ /// returns the output operand it matches.
+ unsigned getMatchedOperand() const;
AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
: InlineAsm::ConstraintInfo(info),
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=57686&r1=57685&r2=57686&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Fri Oct 17 11:21:11 2008
@@ -4363,8 +4363,10 @@
for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
MVT RegisterVT = RegVTs[Value];
- for (unsigned i = 0; i != NumRegs; ++i)
+ for (unsigned i = 0; i != NumRegs; ++i) {
+ assert(Reg < Regs.size() && "Mismatch in # registers expected");
Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
+ }
}
}
@@ -4557,8 +4559,9 @@
const TargetRegisterClass *RC = PhysReg.second;
if (RC) {
// If this is a tied register, our regalloc doesn't know how to maintain
- // the constraint. If it isn't, go ahead and create vreg
- // and let the regalloc do the right thing.
+ // the constraint, so we have to pick a register to pin the input/output to.
+ // If it isn't a matched constraint, go ahead and create vreg and let the
+ // regalloc do its thing.
if (!OpInfo.hasMatchingInput) {
RegVT = *PhysReg.second->vt_begin();
if (OpInfo.ConstraintVT == MVT::Other)
@@ -4785,7 +4788,7 @@
// Second pass - Loop over all of the operands, assigning virtual or physregs
- // to registerclass operands.
+ // to register class operands.
for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
@@ -4860,10 +4863,10 @@
case InlineAsm::isInput: {
SDValue InOperandVal = OpInfo.CallOperand;
- if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
+ if (OpInfo.isMatchingConstraint()) { // Matching constraint?
// If this is required to match an output register we have already set,
// just use its register.
- unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
+ unsigned OperandNo = OpInfo.getMatchedOperand();
// Scan until we find the definition we already emitted of this operand.
// When we find it, create a RegsForValue operand.
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=57686&r1=57685&r2=57686&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Fri Oct 17 11:21:11 2008
@@ -1962,6 +1962,21 @@
//===----------------------------------------------------------------------===//
// Constraint Selection.
+/// isMatchingConstraint - Return true of this is an input operand that is a
+/// matching constraint like "4".
+bool TargetLowering::AsmOperandInfo::isMatchingConstraint() const {
+ assert(!ConstraintCode.empty() && "No known constraint!");
+ return isdigit(ConstraintCode[0]);
+}
+
+/// getMatchedOperand - If this is an input matching constraint, this method
+/// returns the output operand it matches.
+unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
+ assert(!ConstraintCode.empty() && "No known constraint!");
+ return atoi(ConstraintCode.c_str());
+}
+
+
/// getConstraintGenerality - Return an integer indicating how general CT
/// is.
static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
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