[llvm-commits] [llvm] r57612 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td

[Dan Gohman]

Author: djg
Date: Wed Oct 15 19:03:00 2008
New Revision: 57612

URL: http://llvm.org/viewvc/llvm-project?rev=57612&view=rev
Log:
Fix the predicate for memop64 to be a regular load, not just
an unindexed load.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=57612&r1=57611&r2=57612&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Oct 15 19:03:00 2008
@@ -134,7 +134,7 @@
 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
 // 16-byte boundary.
 // FIXME: 8 byte alignment for mmx reads is not required
-def memop64 : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
+def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
   return cast<LoadSDNode>(N)->getAlignment() >= 8;
 }]>;