[llvm-commits] [llvm] r57552 - /llvm/trunk/lib/Target/X86/X86FastISel.cpp
Chris Lattner
sabre at nondot.org
Tue Oct 14 22:07:36 PDT 2008
Author: lattner
Date: Wed Oct 15 00:07:36 2008
New Revision: 57552
URL: http://llvm.org/viewvc/llvm-project?rev=57552&view=rev
Log:
Some minor cleanups:
1. Compute action in X86SelectSelect based on MVT instead of type.
2. Use TLI.getValueType(..) instead of MVT::getVT(..) because the former
handles pointers and the later doesn't.
3. Don't pass TLI into isTypeLegal, since it already has access to it as
an ivar.
#2 gives fast isel some minor new functionality: handling load/stores of
pointers.
Modified:
llvm/trunk/lib/Target/X86/X86FastISel.cpp
Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=57552&r1=57551&r2=57552&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Wed Oct 15 00:07:36 2008
@@ -126,19 +126,15 @@
(VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
}
- bool isTypeLegal(const Type *Ty, const TargetLowering &TLI, MVT &VT,
- bool AllowI1 = false);
+ bool isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1 = false);
};
-bool X86FastISel::isTypeLegal(const Type *Ty, const TargetLowering &TLI,
- MVT &VT, bool AllowI1) {
- VT = MVT::getMVT(Ty, /*HandleUnknown=*/true);
+bool X86FastISel::isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1) {
+ VT = TLI.getValueType(Ty, /*HandleUnknown=*/true);
if (VT == MVT::Other || !VT.isSimple())
// Unhandled type. Halt "fast" selection and bail.
return false;
- if (VT == MVT::iPTR)
- // Use pointer type.
- VT = TLI.getPointerTy();
+
// For now, require SSE/SSE2 for performing floating-point operations,
// since x87 requires additional work.
if (VT == MVT::f64 && !X86ScalarSSEf64)
@@ -484,7 +480,7 @@
/// X86SelectStore - Select and emit code to implement store instructions.
bool X86FastISel::X86SelectStore(Instruction* I) {
MVT VT;
- if (!isTypeLegal(I->getOperand(0)->getType(), TLI, VT))
+ if (!isTypeLegal(I->getOperand(0)->getType(), VT))
return false;
unsigned Val = getRegForValue(I->getOperand(0));
if (Val == 0)
@@ -502,7 +498,7 @@
///
bool X86FastISel::X86SelectLoad(Instruction *I) {
MVT VT;
- if (!isTypeLegal(I->getType(), TLI, VT))
+ if (!isTypeLegal(I->getType(), VT))
return false;
X86AddressMode AM;
@@ -527,7 +523,6 @@
case MVT::f32: return X86::UCOMISSrr;
case MVT::f64: return X86::UCOMISDrr;
}
-
}
/// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS
@@ -579,7 +574,7 @@
CmpInst *CI = cast<CmpInst>(I);
MVT VT;
- if (!isTypeLegal(I->getOperand(0)->getType(), TLI, VT))
+ if (!isTypeLegal(I->getOperand(0)->getType(), VT))
return false;
unsigned ResultReg = createResultReg(&X86::GR8RegClass);
@@ -784,8 +779,8 @@
return false;
}
- MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
- if (VT == MVT::Other || !isTypeLegal(I->getType(), TLI, VT))
+ MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
+ if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
return false;
unsigned Op0Reg = getRegForValue(I->getOperand(0));
@@ -818,29 +813,25 @@
}
bool X86FastISel::X86SelectSelect(Instruction *I) {
- const Type *Ty = I->getType();
- if (isa<PointerType>(Ty))
- Ty = TD.getIntPtrType();
-
+ MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
+ if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
+ return false;
+
unsigned Opc = 0;
const TargetRegisterClass *RC = NULL;
- if (Ty == Type::Int16Ty) {
+ if (VT.getSimpleVT() == MVT::i16) {
Opc = X86::CMOVE16rr;
RC = &X86::GR16RegClass;
- } else if (Ty == Type::Int32Ty) {
+ } else if (VT.getSimpleVT() == MVT::i32) {
Opc = X86::CMOVE32rr;
RC = &X86::GR32RegClass;
- } else if (Ty == Type::Int64Ty) {
+ } else if (VT.getSimpleVT() == MVT::i64) {
Opc = X86::CMOVE64rr;
RC = &X86::GR64RegClass;
} else {
return false;
}
- MVT VT = MVT::getMVT(Ty, /*HandleUnknown=*/true);
- if (VT == MVT::Other || !isTypeLegal(Ty, TLI, VT))
- return false;
-
unsigned Op0Reg = getRegForValue(I->getOperand(0));
if (Op0Reg == 0) return false;
unsigned Op1Reg = getRegForValue(I->getOperand(1));
@@ -856,17 +847,16 @@
}
bool X86FastISel::X86SelectFPExt(Instruction *I) {
- if (Subtarget->hasSSE2()) {
- if (I->getType() == Type::DoubleTy) {
- Value *V = I->getOperand(0);
- if (V->getType() == Type::FloatTy) {
- unsigned OpReg = getRegForValue(V);
- if (OpReg == 0) return false;
- unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
- BuildMI(MBB, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg);
- UpdateValueMap(I, ResultReg);
- return true;
- }
+ // fpext from float to double.
+ if (Subtarget->hasSSE2() && I->getType() == Type::DoubleTy) {
+ Value *V = I->getOperand(0);
+ if (V->getType() == Type::FloatTy) {
+ unsigned OpReg = getRegForValue(V);
+ if (OpReg == 0) return false;
+ unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
+ BuildMI(MBB, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg);
+ UpdateValueMap(I, ResultReg);
+ return true;
}
}
@@ -958,7 +948,7 @@
MVT RetVT;
if (RetTy == Type::VoidTy)
RetVT = MVT::isVoid;
- else if (!isTypeLegal(RetTy, TLI, RetVT, true))
+ else if (!isTypeLegal(RetTy, RetVT, true))
return false;
// Materialize callee address in a register. FIXME: GV address can be
@@ -1012,7 +1002,7 @@
const Type *ArgTy = (*i)->getType();
MVT ArgVT;
- if (!isTypeLegal(ArgTy, TLI, ArgVT))
+ if (!isTypeLegal(ArgTy, ArgVT))
return false;
unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
Flags.setOrigAlign(OriginalAlignment);
@@ -1065,7 +1055,7 @@
Arg, ArgVT, Arg);
if (!Emitted)
Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
- Arg, ArgVT, Arg);
+ Arg, ArgVT, Arg);
if (!Emitted)
Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
Arg, ArgVT, Arg);
@@ -1217,7 +1207,7 @@
unsigned X86FastISel::TargetMaterializeConstant(Constant *C) {
MVT VT;
- if (!isTypeLegal(C->getType(), TLI, VT))
+ if (!isTypeLegal(C->getType(), VT))
return false;
// Get opcode and regclass of the output for the given load instruction.
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