[llvm-commits] [llvm] r57458 - in /llvm/trunk: lib/CodeGen/SimpleRegisterCoalescing.cpp test/CodeGen/X86/2008-10-13-CoalescerBug.ll

[Evan Cheng]

Author: evancheng
Date: Mon Oct 13 13:35:52 2008
New Revision: 57458

URL: http://llvm.org/viewvc/llvm-project?rev=57458&view=rev
Log:
Also update sub-register intervals after a trivial computation is rematt'ed for a copy instruction. PR2775.

Added:
    llvm/trunk/test/CodeGen/X86/2008-10-13-CoalescerBug.ll
Modified:
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=57458&r1=57457&r2=57458&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Mon Oct 13 13:35:52 2008
@@ -460,6 +460,16 @@
   unsigned DefIdx = li_->getDefIndex(CopyIdx);
   const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
   DLR->valno->copy = NULL;
+  // Don't forget to update sub-register intervals.
+  if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
+    for (const unsigned* SR = tri_->getSubRegisters(DstReg); *SR; ++SR) {
+      if (!li_->hasInterval(*SR))
+        continue;
+      DLR = li_->getInterval(*SR).getLiveRangeContaining(DefIdx);
+      if (DLR && DLR->valno->copy == CopyMI)
+        DLR->valno->copy = NULL;
+    }
+  }
 
   MachineBasicBlock::iterator MII = CopyMI;
   MachineBasicBlock *MBB = CopyMI->getParent();

Added: llvm/trunk/test/CodeGen/X86/2008-10-13-CoalescerBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-10-13-CoalescerBug.ll?rev=57458&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-10-13-CoalescerBug.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2008-10-13-CoalescerBug.ll Mon Oct 13 13:35:52 2008
@@ -0,0 +1,42 @@
+; RUN: llvm-as < %s | llc -march=x86
+; PR2775
+
+define i32 @func_77(i8 zeroext %p_79) nounwind {
+entry:
+	%0 = tail call i32 (...)* @func_43(i32 1) nounwind		; <i32> [#uses=1]
+	%1 = icmp eq i32 %0, 0		; <i1> [#uses=1]
+	br i1 %1, label %bb3, label %bb
+
+bb:		; preds = %entry
+	br label %bb3
+
+bb3:		; preds = %bb, %entry
+	%p_79_addr.0 = phi i8 [ 0, %bb ], [ %p_79, %entry ]		; <i8> [#uses=1]
+	%2 = zext i8 %p_79_addr.0 to i32		; <i32> [#uses=2]
+	%3 = zext i1 false to i32		; <i32> [#uses=2]
+	%4 = tail call i32 (...)* @rshift_u_s(i32 1) nounwind		; <i32> [#uses=0]
+	%5 = lshr i32 %2, %2		; <i32> [#uses=3]
+	%6 = icmp eq i32 0, 0		; <i1> [#uses=1]
+	br i1 %6, label %bb6, label %bb9
+
+bb6:		; preds = %bb3
+	%7 = ashr i32 %5, %3		; <i32> [#uses=1]
+	%8 = icmp eq i32 %7, 0		; <i1> [#uses=1]
+	%9 = select i1 %8, i32 %3, i32 0		; <i32> [#uses=1]
+	%. = shl i32 %5, %9		; <i32> [#uses=1]
+	br label %bb9
+
+bb9:		; preds = %bb6, %bb3
+	%.0 = phi i32 [ %., %bb6 ], [ %5, %bb3 ]		; <i32> [#uses=0]
+	br i1 false, label %return, label %bb10
+
+bb10:		; preds = %bb9
+	ret i32 undef
+
+return:		; preds = %bb9
+	ret i32 undef
+}
+
+declare i32 @func_43(...)
+
+declare i32 @rshift_u_s(...)