[llvm-commits] [llvm] r57266 - /llvm/trunk/lib/Target/X86/X86FastISel.cpp

[Dan Gohman]

Author: djg
Date: Tue Oct  7 17:10:33 2008
New Revision: 57266

URL: http://llvm.org/viewvc/llvm-project?rev=57266&view=rev
Log:
Add MBB successors and physreg Uses in the same order that
SDISel typically adds them in. This makes it a little easier
to compare FastISel output with SDISel output.

Modified:
    llvm/trunk/lib/Target/X86/X86FastISel.cpp

Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=57266&r1=57265&r2=57266&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Tue Oct  7 17:10:33 2008
@@ -784,8 +784,8 @@
       default:
         return false;
       }
-      MBB->addSuccessor(TrueMBB);
       FastEmitBranch(FalseMBB);
+      MBB->addSuccessor(TrueMBB);
       return true;
     }
   }
@@ -797,9 +797,8 @@
   BuildMI(MBB, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
 
   BuildMI(MBB, TII.get(X86::JNE)).addMBB(TrueMBB);
-  MBB->addSuccessor(TrueMBB);
-
   FastEmitBranch(FalseMBB);
+  MBB->addSuccessor(TrueMBB);
 
   return true;
 }
@@ -1180,10 +1179,8 @@
     MIB.addReg(X86::EBX);
 
   // Add implicit physical register uses to the call.
-  while (!RegArgs.empty()) {
-    MIB.addReg(RegArgs.back());
-    RegArgs.pop_back();
-  }
+  for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
+    MIB.addReg(RegArgs[i]);
 
   // Issue CALLSEQ_END
   unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();