[llvm-commits] [llvm] r57027 - in /llvm/trunk/lib: CodeGen/SelectionDAG/LegalizeDAG.cpp Target/X86/X86ISelDAGToDAG.cpp Target/X86/X86ISelLowering.cpp Target/X86/X86InstrInfo.td
Dale Johannesen
dalej at apple.com
Fri Oct 3 12:41:08 PDT 2008
Author: johannes
Date: Fri Oct 3 14:41:08 2008
New Revision: 57027
URL: http://llvm.org/viewvc/llvm-project?rev=57027&view=rev
Log:
Pass MemOperand through for 64-bit atomics on 32-bit,
incidentally making the case where the memop is a
pointer deref work. Fix cmp-and-swap regression.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86InstrInfo.td
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=57027&r1=57026&r2=57027&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Oct 3 14:41:08 2008
@@ -6212,20 +6212,33 @@
break;
}
+ case ISD::ATOMIC_CMP_SWAP_64: {
+ // This operation does not need a loop.
+ SDValue Tmp = TLI.LowerOperation(Op, DAG);
+ assert(Tmp.getNode() && "Node must be custom expanded!");
+ ExpandOp(Tmp.getValue(0), Lo, Hi);
+ AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
+ LegalizeOp(Tmp.getValue(1)));
+ break;
+ }
+
case ISD::ATOMIC_LOAD_ADD_64:
case ISD::ATOMIC_LOAD_SUB_64:
case ISD::ATOMIC_LOAD_AND_64:
case ISD::ATOMIC_LOAD_OR_64:
case ISD::ATOMIC_LOAD_XOR_64:
case ISD::ATOMIC_LOAD_NAND_64:
- case ISD::ATOMIC_SWAP_64:
- case ISD::ATOMIC_CMP_SWAP_64: {
+ case ISD::ATOMIC_SWAP_64: {
+ // These operations require a loop to be generated. We can't do that yet,
+ // so substitute a target-dependent pseudo and expand that later.
SDValue In2Lo, In2Hi, In2;
ExpandOp(Op.getOperand(2), In2Lo, In2Hi);
In2 = DAG.getNode(ISD::BUILD_PAIR, VT, In2Lo, In2Hi);
- SDValue Result = TLI.LowerOperation(
- DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), Op.getOperand(1), In2),
- DAG);
+ AtomicSDNode* Anode = cast<AtomicSDNode>(Node);
+ SDValue Replace =
+ DAG.getAtomic(Op.getOpcode(), Op.getOperand(0), Op.getOperand(1), In2,
+ Anode->getSrcValue(), Anode->getAlignment());
+ SDValue Result = TLI.LowerOperation(Replace, DAG);
ExpandOp(Result.getValue(0), Lo, Hi);
// Remember that we legalized the chain.
AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1)));
Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=57027&r1=57026&r2=57027&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Oct 3 14:41:08 2008
@@ -1209,14 +1209,15 @@
SDValue Tmp0, Tmp1, Tmp2, Tmp3;
if (!SelectAddr(In1, In1, Tmp0, Tmp1, Tmp2, Tmp3))
return NULL;
+ SDValue LSI = Node->getOperand(4); // MemOperand
AddToISelQueue(Tmp0);
AddToISelQueue(Tmp1);
AddToISelQueue(Tmp2);
AddToISelQueue(Tmp3);
AddToISelQueue(In2L);
AddToISelQueue(In2H);
+ // For now, don't select the MemOperand object, we don't know how.
AddToISelQueue(Chain);
- SDValue LSI = CurDAG->getMemOperand(cast<MemSDNode>(In1)->getMemOperand());
const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, In2L, In2H, LSI, Chain };
return CurDAG->getTargetNode(Opc, MVT::i32, MVT::i32, MVT::Other, Ops, 8);
}
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=57027&r1=57026&r2=57027&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Oct 3 14:41:08 2008
@@ -6026,9 +6026,12 @@
assert(Node->getOperand(2).getNode()->getOpcode()==ISD::BUILD_PAIR);
SDValue In2L = Node->getOperand(2).getNode()->getOperand(0);
SDValue In2H = Node->getOperand(2).getNode()->getOperand(1);
- SDValue Ops[] = { Chain, In1, In2L, In2H };
+ // This is a generalized SDNode, not an AtomicSDNode, so it doesn't
+ // have a MemOperand. Pass the info through as a normal operand.
+ SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
+ SDValue Ops[] = { Chain, In1, In2L, In2H, LSI };
SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
- SDValue Result = DAG.getNode(NewOp, Tys, Ops, 4);
+ SDValue Result = DAG.getNode(NewOp, Tys, Ops, 5);
SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
SDValue ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2);
SDValue Vals[2] = { ResultVal, Result.getValue(2) };
@@ -6415,7 +6418,7 @@
return nextMBB;
}
-// private utility function
+// private utility function: 64 bit atomics on 32 bit host.
MachineBasicBlock *
X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
MachineBasicBlock *MBB,
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=57027&r1=57026&r2=57027&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Fri Oct 3 14:41:08 2008
@@ -2752,6 +2752,7 @@
let Constraints = "$val1 = $dst1, $val2 = $dst2",
Defs = [EFLAGS, EAX, EBX, ECX, EDX],
Uses = [EAX, EBX, ECX, EDX],
+ mayLoad = 1, mayStore = 1,
usesCustomDAGSchedInserter = 1 in {
def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
(ins i64mem:$ptr, GR32:$val1, GR32:$val2),
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