[llvm-commits] [llvm] r56600 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td

[Evan Cheng]

Author: evancheng
Date: Wed Sep 24 19:49:51 2008
New Revision: 56600

URL: http://llvm.org/viewvc/llvm-project?rev=56600&view=rev
Log:
pmovsxbq etc. requires sse4.1.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=56600&r1=56599&r2=56600&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Sep 24 19:49:51 2008
@@ -3442,14 +3442,14 @@
 
 // Common patterns involving scalar load
 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
-          (PMOVSXBDrm addr:$src)>;
+          (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
-          (PMOVSXWQrm addr:$src)>;
+          (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
 
 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
-          (PMOVZXBDrm addr:$src)>;
+          (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
-          (PMOVZXWQrm addr:$src)>;
+          (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
 
 
 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
@@ -3472,12 +3472,12 @@
 def : Pat<(int_x86_sse41_pmovsxbq
             (bitconvert (v4i32 (X86vzmovl
                              (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
-          (PMOVSXBQrm addr:$src)>;
+          (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
 
 def : Pat<(int_x86_sse41_pmovzxbq
             (bitconvert (v4i32 (X86vzmovl
                              (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
-          (PMOVZXBQrm addr:$src)>;
+          (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
 
 
 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem