[llvm-commits] [llvm] r56384 - in /llvm/trunk/lib/CodeGen: RegAllocLinearScan.cpp SimpleRegisterCoalescing.cpp

[Dale Johannesen]

On Sep 23, 2008, at 4:27 PMPDT, Evan Cheng wrote:

>
> On Sep 23, 2008, at 3:17 PM, Dale Johannesen wrote:
>>>
>>
>> This did basically Just Work (I haven't run the gcc testsuite yet,  
>> but
>> it doesn't break anything in
>> the llvm testsuite and fixes all the examples in our bug reports.)
>> Unfortunately, this approach
>> only works in the linear scan RA, while we use a different RA with -
>> O0.... I guess I need to fix
>> that before turning it on.
>
> Yay. Good thing I was wrong. :-) Would you like to add the support
> that allows us to model it as operand constraint so we can test it on
> more things?

Are you talking about the "minor tblgen and TargetInstrDesc changes"
described below?   Not sure I understand how that would work, and I
don't really want to wait for it before checking in.

> Evan
>
>>
>>
>>> Owen, can your liveintervals renumbering work be impacted?
>>> i.e. Does it assume def must be one cycle before use?
>>>
>>>>
>>>>
>>>>>> Can earlyclobber operands be used to model the armv4 "mul"
>>>>>> register
>>>>>> weirdness where the input and output regs can't be the same?
>>>>>
>>>>> We could, but the correct way to model it is to push the use down
>>>>> one
>>>>> cycle, not def up one cycle. The problem with early clobber is the
>>>>> def
>>>>> cannot overlap any of the uses (both Rm and Rs). In the ARM mul
>>>>> case,
>>>>> the def cannot overlap Rm only.
>>>>
>>>> Sure, I agree with that.  This is also true of most inline asms  
>>>> with
>>>> multiple instructions (like the example I gave).  Using  
>>>> earlyclobber
>>>> should be a conservative but correct solution (and much better than
>>>> using the 'multiply fixer' pass that used to exist).
>>>>
>>>> This would also make it easier to test that earlyclobber is working
>>>> right (multiplies are more frequent than & in asms), which is why I
>>>> brought it up. :)
>>>
>>> That will require some minor tblgen and TargetInstrDesc changes. If
>>> someone want to do that, sure.
>>>
>>> Evan
>>>
>>>>
>>>>
>>>> -Chris
>>>>
>>>> _______________________________________________
>>>> llvm-commits mailing list
>>>> llvm-commits at cs.uiuc.edu
>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits