[llvm-commits] [llvm] r56384 - in /llvm/trunk/lib/CodeGen: RegAllocLinearScan.cpp SimpleRegisterCoalescing.cpp
Chris Lattner
clattner at apple.com
Sun Sep 21 23:19:20 PDT 2008
On Sep 21, 2008, at 11:17 PM, Evan Cheng wrote:
>>> While that's the correct approach, it breaks all kinds of
>>> assumptions
>>> in liveintervals and the coalescer. It will make the problem much
>>> more
>>> complicated. I don't think it's worth the effort.
>>
>> What sorts of assumptions?
>
> That use must be 1 cycle after instruction cycle, def must be 2 cycles
> after it.
What code makes this sort of assumption? It seems fragile.
>> It typically doesn't have anything to do with a micro architecture,
>> it
>> has to do with the fact that an inline asm has multiple instructions.
>> For example if you had an inline asm with:
>>
>> "$out0 = inst1 $in1, 4
>> $out1 = inst2 $in2, 142"
>>
>> Then you'd have to mark $out0 as being an early clobber, because it
>> is
>> stored to before $in2 is read.
>
> Ewwww.
Eww what? You don't like asms with multiple instructions? Or you
prefer CPUs that have instructions that would require this? ;-)
-Chris
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