[llvm-commits] [llvm] r55558 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/Target/X86/X86Instr64bit.td lib/Target/X86/X86InstrInfo.td test/CodeGen/X86/shift-and.ll
Chris Lattner
clattner at apple.com
Sun Sep 21 12:12:11 PDT 2008
On Aug 29, 2008, at 7:03 PM, Evan Cheng wrote:
> Author: evancheng
> Date: Fri Aug 29 21:03:58 2008
> New Revision: 55558
>
> URL: http://llvm.org/viewvc/llvm-project?rev=55558&view=rev
> Log:
> Transform (x << (y&31)) -> (x << y). This takes advantage of the
> fact x86 shift instructions 2nd operand (shift count) is limited to
> 0 to 31 (or 63 in the x86-64 case).
Ok, cool.
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Aug 29
> 21:03:58 2008
> @@ -2310,6 +2310,26 @@
> if (DAG.MaskedValueIsZero(SDValue(N, 0),
>
> APInt::getAllOnesValue(VT.getSizeInBits())))
> return DAG.getConstant(0, VT);
> + // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), c))
> + // iff (trunc c) == c
Three things:
1) I don't think it matters if (trunc c) == c. The bits that don't
match will get discarded anyway.
2) I think you should check that the trunc and and only have a single
use. If they don't, you could introduce extra computations of these
values.
3) If the body of the dag combine is more than a couple lines, please
introduce a helper function so that the SHL/SRA/SRL cases aren't all
copies of each other.
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
> +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Fri Aug 29 21:03:58
> 2008
> @@ -1341,6 +1341,22 @@
> // (shl x, 1) ==> (add x, x)
> def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
>
> +// (shl x (and y, 63)) ==> (shl x, y)
> +def : Pat<(shl GR64:$src1, (and CL:$amt, 63)),
> + (SHL64rCL GR64:$src1)>;
> +def : Pat<(store (shl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:
> $dst),
> + (SHL64mCL addr:$dst)>;
nice!
-Chris
More information about the llvm-commits
mailing list