[llvm-commits] [llvm] r56326 - in /llvm/trunk: include/llvm/CodeGen/LiveInterval.h include/llvm/CodeGen/LiveIntervalAnalysis.h lib/CodeGen/LiveInterval.cpp lib/CodeGen/LiveIntervalAnalysis.cpp lib/CodeGen/RegAllocLinearScan.cpp

[Dale Johannesen]

On Sep 19, 2008, at 11:04 AMPDT, Evan Cheng wrote:

>
> On Sep 19, 2008, at 10:50 AM, Dale Johannesen wrote:
>
>>
>> On Sep 19, 2008, at 10:48 AMPDT, Evan Cheng wrote:
>>>>
>>>>  float weight;        // weight of this interval
>>>> +    bool isEarlyClobber;
>>>> +    bool overlapsEarlyClobber;
>>>
>>> Hi Dale,
>>>
>>> I don't think we want two bits. I'd rather go with one bit and have
>>> register allocator look at both use and def operands. What do you
>>> think?
>>
>> The comment explains why I don't want to do this:
>
> Sorry, I don't follow. Can you provide an example?

void foo (int x, int y) {
   int z=x+y;
   int w=x+y;
   int t;
   asm volatile ("%0 %1 %2" : "=&r"(t) : "r"(z), "r"(w));
}

%1 and %2 can share a register, but if there is no way to distinguish  
between earlyclobber and overlaps-earlyclobber, we can't do this.
In theory this is a matter of correctness, it is possible to construct  
cases where you run out of registers if you don't share.