[llvm-commits] [llvm] r56176 - in /llvm/trunk/lib/Target/ARM: ARMCodeEmitter.cpp ARMInstrFormats.td ARMInstrInfo.h ARMInstrInfo.td
Evan Cheng
evan.cheng at apple.com
Fri Sep 12 16:15:39 PDT 2008
Author: evancheng
Date: Fri Sep 12 18:15:39 2008
New Revision: 56176
URL: http://llvm.org/viewvc/llvm-project?rev=56176&view=rev
Log:
Eliminate unnecessary instruction formats.
Modified:
llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
llvm/trunk/lib/Target/ARM/ARMInstrInfo.h
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=56176&r1=56175&r2=56176&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Fri Sep 12 18:15:39 2008
@@ -338,34 +338,22 @@
unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
const TargetInstrDesc &TID,
unsigned Binary) {
- if (MI.getOpcode() == ARM::MOVi2pieces)
- // FIXME.
- abort();
+ if ((TID.TSFlags & ARMII::FormMask) != ARMII::Pseudo)
+ abort(); // FIXME
// Encode S bit if MI modifies CPSR.
Binary |= getAddrMode1SBit(MI, TID);
- unsigned Format = TID.TSFlags & ARMII::FormMask;
- // FIXME: Consolidate into a single bit.
- bool isUnary = (Format == ARMII::DPRdMisc ||
- Format == ARMII::DPRdIm ||
- Format == ARMII::DPRdReg ||
- Format == ARMII::DPRdSoReg ||
- Format == ARMII::DPRnIm ||
- Format == ARMII::DPRnReg ||
- Format == ARMII::DPRnSoReg);
-
- unsigned OpIdx = 0;
-
// Encode register def if there is one.
unsigned NumDefs = TID.getNumDefs();
+ unsigned OpIdx = 0;
if (NumDefs) {
Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdShift;
++OpIdx;
}
// Encode first non-shifter register operand if ther is one.
- if (!isUnary) {
+ if ((TID.TSFlags & ARMII::FormMask) != ARMII::UnaryFrm) {
Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
++OpIdx;
}
Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=56176&r1=56175&r2=56176&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Sep 12 18:15:39 2008
@@ -28,26 +28,15 @@
def Branch : Format<7>;
def BranchMisc : Format<8>;
-def DPRdIm : Format<9>;
-def DPRdReg : Format<10>;
-def DPRdSoReg : Format<11>;
-def DPRdMisc : Format<12>;
-def DPRnIm : Format<13>;
-def DPRnReg : Format<14>;
-def DPRnSoReg : Format<15>;
-def DPRIm : Format<16>;
-def DPRReg : Format<17>;
-def DPRSoReg : Format<18>;
-def DPRImS : Format<19>;
-def DPRRegS : Format<20>;
-def DPRSoRegS : Format<21>;
-
-def LdFrm : Format<22>;
-def StFrm : Format<23>;
-
-def ArithMisc : Format<24>;
-def ThumbFrm : Format<25>;
-def VFPFrm : Format<26>;
+def UnaryFrm : Format<9>;
+def BinaryFrm : Format<10>;
+
+def LdFrm : Format<11>;
+def StFrm : Format<12>;
+
+def ArithMisc : Format<13>;
+def ThumbFrm : Format<14>;
+def VFPFrm : Format<15>;
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.h?rev=56176&r1=56175&r2=56176&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.h Fri Sep 12 18:15:39 2008
@@ -82,35 +82,21 @@
BranchMisc = 8 << FormShift,
// Data Processing instructions
- DPRdIm = 9 << FormShift,
- DPRdReg = 10 << FormShift,
- DPRdSoReg = 11 << FormShift,
- DPRdMisc = 12 << FormShift,
-
- DPRnIm = 13 << FormShift,
- DPRnReg = 14 << FormShift,
- DPRnSoReg = 15 << FormShift,
-
- DPRIm = 16 << FormShift,
- DPRReg = 17 << FormShift,
- DPRSoReg = 18 << FormShift,
-
- DPRImS = 19 << FormShift,
- DPRRegS = 20 << FormShift,
- DPRSoRegS = 21 << FormShift,
+ UnaryFrm = 9 << FormShift,
+ BinaryFrm = 10 << FormShift,
// Load and Store
- LdFrm = 22 << FormShift,
- StFrm = 23 << FormShift,
+ LdFrm = 11 << FormShift,
+ StFrm = 12 << FormShift,
// Miscellaneous arithmetic instructions
- ArithMisc = 24 << FormShift,
+ ArithMisc = 13 << FormShift,
// Thumb format
- ThumbFrm = 25 << FormShift,
+ ThumbFrm = 14 << FormShift,
// VFP format
- VPFFrm = 26 << FormShift,
+ VPFFrm = 15 << FormShift,
// Field shifts - such shifts are used to set field while generating
// machine instructions.
@@ -118,10 +104,8 @@
RegRsShift = 8,
RegRdShift = 12,
RegRnShift = 16,
- L_BitShift = 20,
S_BitShift = 20,
U_BitShift = 23,
- IndexShift = 24,
I_BitShift = 25
};
}
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=56176&r1=56175&r2=56176&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Sep 12 18:15:39 2008
@@ -344,13 +344,13 @@
/// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
/// binop that produces a value.
multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode> {
- def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
+ def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), BinaryFrm,
opc, " $dst, $a, $b",
[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
- def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPRReg,
+ def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), BinaryFrm,
opc, " $dst, $a, $b",
[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
- def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
+ def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), BinaryFrm,
opc, " $dst, $a, $b",
[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
}
@@ -359,13 +359,13 @@
/// instruction modifies the CSPR register.
let Defs = [CPSR] in {
multiclass ASI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode> {
- def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRImS,
+ def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), BinaryFrm,
opc, "s $dst, $a, $b",
[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
- def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPRRegS,
+ def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), BinaryFrm,
opc, "s $dst, $a, $b",
[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
- def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoRegS,
+ def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), BinaryFrm,
opc, "s $dst, $a, $b",
[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
}
@@ -376,13 +376,13 @@
/// a explicit result, only implicitly set CPSR.
let Defs = [CPSR] in {
multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
- def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPRnIm,
+ def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), UnaryFrm,
opc, " $a, $b",
[(opnode GPR:$a, so_imm:$b)]>;
- def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPRnReg,
+ def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), UnaryFrm,
opc, " $a, $b",
[(opnode GPR:$a, GPR:$b)]>;
- def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPRnSoReg,
+ def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), UnaryFrm,
opc, " $a, $b",
[(opnode GPR:$a, so_reg:$b)]>;
}
@@ -419,13 +419,13 @@
let Uses = [CPSR] in {
multiclass AsXI1_bin_c_irs<bits<4> opcod, string opc, PatFrag opnode> {
def ri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
- DPRIm, !strconcat(opc, "${s} $dst, $a, $b"),
+ BinaryFrm, !strconcat(opc, "${s} $dst, $a, $b"),
[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
def rr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, cc_out:$s),
- DPRReg, !strconcat(opc, "${s} $dst, $a, $b"),
+ BinaryFrm, !strconcat(opc, "${s} $dst, $a, $b"),
[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
def rs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
- DPRSoReg, !strconcat(opc, "${s} $dst, $a, $b"),
+ BinaryFrm, !strconcat(opc, "${s} $dst, $a, $b"),
[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
}
}
@@ -743,16 +743,16 @@
// Move Instructions.
//
-def MOVr : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdReg,
+def MOVr : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), UnaryFrm,
"mov", " $dst, $src", []>;
-def MOVs : AsI1<0xD, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg,
+def MOVs : AsI1<0xD, (outs GPR:$dst), (ins so_reg:$src), UnaryFrm,
"mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>;
let isReMaterializable = 1 in
-def MOVi : AsI1<0xD, (outs GPR:$dst), (ins so_imm:$src), DPRdIm,
+def MOVi : AsI1<0xD, (outs GPR:$dst), (ins so_imm:$src), UnaryFrm,
"mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>;
-def MOVrx : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
+def MOVrx : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), UnaryFrm,
"mov", " $dst, $src, rrx",
[(set GPR:$dst, (ARMrrx GPR:$src))]>;
@@ -760,10 +760,10 @@
// due to flag operands.
let Defs = [CPSR] in {
-def MOVsrl_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
+def MOVsrl_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), UnaryFrm,
"mov", "s $dst, $src, lsr #1",
[(set GPR:$dst, (ARMsrl_flag GPR:$src))]>;
-def MOVsra_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
+def MOVsra_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), UnaryFrm,
"mov", "s $dst, $src, asr #1",
[(set GPR:$dst, (ARMsra_flag GPR:$src))]>;
}
@@ -823,20 +823,20 @@
defm SBC : AsXI1_bin_c_irs<0x6, "sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
// These don't define reg/reg forms, because they are handled above.
-def RSBri : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
+def RSBri : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), BinaryFrm,
"rsb", " $dst, $a, $b",
[(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>;
-def RSBrs : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
+def RSBrs : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), BinaryFrm,
"rsb", " $dst, $a, $b",
[(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
// RSB with 's' bit set.
let Defs = [CPSR] in {
-def RSBSri : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
+def RSBSri : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), BinaryFrm,
"rsb", "s $dst, $a, $b",
[(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>;
-def RSBSrs : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
+def RSBSrs : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), BinaryFrm,
"rsb", "s $dst, $a, $b",
[(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
}
@@ -844,10 +844,10 @@
// FIXME: Do not allow RSC to be predicated for now. But they can set CPSR.
let Uses = [CPSR] in {
def RSCri : AXI1<0x7, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
- DPRIm, "rsc${s} $dst, $a, $b",
+ BinaryFrm, "rsc${s} $dst, $a, $b",
[(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>;
def RSCrs : AXI1<0x7, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
- DPRSoReg, "rsc${s} $dst, $a, $b",
+ BinaryFrm, "rsc${s} $dst, $a, $b",
[(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>;
}
@@ -876,12 +876,12 @@
defm EOR : AsI1_bin_irs<0x1, "eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
defm BIC : AsI1_bin_irs<0xE, "bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
-def MVNr : AsI1<0xE, (outs GPR:$dst), (ins GPR:$src), DPRdReg,
+def MVNr : AsI1<0xE, (outs GPR:$dst), (ins GPR:$src), UnaryFrm,
"mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>;
-def MVNs : AsI1<0xE, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg,
+def MVNs : AsI1<0xE, (outs GPR:$dst), (ins so_reg:$src), UnaryFrm,
"mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>;
let isReMaterializable = 1 in
-def MVNi : AsI1<0xE, (outs GPR:$dst), (ins so_imm:$imm), DPRdIm,
+def MVNi : AsI1<0xE, (outs GPR:$dst), (ins so_imm:$imm), UnaryFrm,
"mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>;
def : ARMPat<(and GPR:$src, so_imm_not:$imm),
@@ -1107,17 +1107,17 @@
// FIXME: should be able to write a pattern for ARMcmov, but can't use
// a two-value operand where a dag node expects two operands. :(
def MOVCCr : AI<0xD, (outs GPR:$dst), (ins GPR:$false, GPR:$true),
- DPRdReg, "mov", " $dst, $true",
+ UnaryFrm, "mov", " $dst, $true",
[/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst">;
def MOVCCs : AI<0xD, (outs GPR:$dst), (ins GPR:$false, so_reg:$true),
- DPRdSoReg, "mov", " $dst, $true",
+ UnaryFrm, "mov", " $dst, $true",
[/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst">;
def MOVCCi : AI<0xD, (outs GPR:$dst), (ins GPR:$false, so_imm:$true),
- DPRdIm, "mov", " $dst, $true",
+ UnaryFrm, "mov", " $dst, $true",
[/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst">;
@@ -1165,7 +1165,7 @@
// Two piece so_imms.
let isReMaterializable = 1 in
-def MOVi2pieces : AI1x2<0x0, (outs GPR:$dst), (ins so_imm2part:$src), DPRdMisc,
+def MOVi2pieces : AI1x2<0x0, (outs GPR:$dst), (ins so_imm2part:$src), Pseudo,
"mov", " $dst, $src",
[(set GPR:$dst, so_imm2part:$src)]>;
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