[llvm-commits] [llvm] r55925 - in /llvm/trunk: lib/Target/X86/X86FastISel.cpp test/CodeGen/X86/fast-isel-call.ll
Evan Cheng
evan.cheng at apple.com
Mon Sep 8 10:15:42 PDT 2008
Author: evancheng
Date: Mon Sep 8 12:15:42 2008
New Revision: 55925
URL: http://llvm.org/viewvc/llvm-project?rev=55925&view=rev
Log:
Handle calls which produce i1 results: promote to i8 but and it with 1 to get the low bit.
Added:
llvm/trunk/test/CodeGen/X86/fast-isel-call.ll
Modified:
llvm/trunk/lib/Target/X86/X86FastISel.cpp
Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=55925&r1=55924&r2=55925&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Mon Sep 8 12:15:42 2008
@@ -107,7 +107,8 @@
};
-static bool isTypeLegal(const Type *Ty, const TargetLowering &TLI, MVT &VT) {
+static bool isTypeLegal(const Type *Ty, const TargetLowering &TLI, MVT &VT,
+ bool AllowI1 = false) {
VT = MVT::getMVT(Ty, /*HandleUnknown=*/true);
if (VT == MVT::Other || !VT.isSimple())
// Unhandled type. Halt "fast" selection and bail.
@@ -119,7 +120,7 @@
// selector contains all of the 64-bit instructions from x86-64,
// under the assumption that i64 won't be used if the target doesn't
// support it.
- return TLI.isTypeLegal(VT);
+ return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
}
#include "X86GenCallingConv.inc"
@@ -701,9 +702,16 @@
// Handle *simple* calls for now.
const Type *RetTy = CS.getType();
MVT RetVT;
- if (!isTypeLegal(RetTy, TLI, RetVT))
+ if (!isTypeLegal(RetTy, TLI, RetVT, true))
return false;
+ // Allow calls which produce i1 results.
+ bool AndToI1 = false;
+ if (RetVT == MVT::i1) {
+ RetVT = MVT::i8;
+ AndToI1 = true;
+ }
+
// Deal with call operands first.
SmallVector<unsigned, 4> Args;
SmallVector<MVT, 4> ArgVTs;
@@ -859,6 +867,13 @@
addFrameReference(BuildMI(MBB, TII.get(Opc), ResultReg), FI);
}
+ if (AndToI1) {
+ // Mask out all but lowest bit for some call which produces an i1.
+ unsigned AndResult = createResultReg(X86::GR8RegisterClass);
+ BuildMI(MBB, TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1);
+ ResultReg = AndResult;
+ }
+
UpdateValueMap(I, ResultReg);
}
Added: llvm/trunk/test/CodeGen/X86/fast-isel-call.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-call.ll?rev=55925&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-call.ll (added)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-call.ll Mon Sep 8 12:15:42 2008
@@ -0,0 +1,13 @@
+; RUN: llvm-as < %s | llc -fast-isel -march=x86 | grep and
+
+define i32 @t() nounwind {
+tak:
+ %tmp = call i1 @foo()
+ br i1 %tmp, label %BB1, label %BB2
+BB1:
+ ret i32 1
+BB2:
+ ret i32 0
+}
+
+declare i1 @foo() zeroext nounwind
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