[llvm-commits] [llvm] r55855 - /llvm/trunk/lib/Target/X86/X86FastISel.cpp

[Dan Gohman]

Author: djg
Date: Fri Sep  5 16:13:04 2008
New Revision: 55855

URL: http://llvm.org/viewvc/llvm-project?rev=55855&view=rev
Log:
Fix the opcodes used by X86FastISel for shifts and conditional moves.

Modified:
    llvm/trunk/lib/Target/X86/X86FastISel.cpp

Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=55855&r1=55854&r2=55855&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Fri Sep  5 16:13:04 2008
@@ -468,36 +468,36 @@
     CReg = X86::CL;
     RC = &X86::GR8RegClass;
     switch (I->getOpcode()) {
-    case Instruction::LShr: Opc = X86::SHL8rCL; break;
+    case Instruction::LShr: Opc = X86::SHR8rCL; break;
     case Instruction::AShr: Opc = X86::SAR8rCL; break;
-    case Instruction::Shl:  Opc = X86::SHR8rCL; break;
+    case Instruction::Shl:  Opc = X86::SHL8rCL; break;
     default: return false;
     }
   } else if (I->getType() == Type::Int16Ty) {
     CReg = X86::CX;
     RC = &X86::GR16RegClass;
     switch (I->getOpcode()) {
-    case Instruction::LShr: Opc = X86::SHL16rCL; break;
+    case Instruction::LShr: Opc = X86::SHR16rCL; break;
     case Instruction::AShr: Opc = X86::SAR16rCL; break;
-    case Instruction::Shl:  Opc = X86::SHR16rCL; break;
+    case Instruction::Shl:  Opc = X86::SHL16rCL; break;
     default: return false;
     }
   } else if (I->getType() == Type::Int32Ty) {
     CReg = X86::ECX;
     RC = &X86::GR32RegClass;
     switch (I->getOpcode()) {
-    case Instruction::LShr: Opc = X86::SHL32rCL; break;
+    case Instruction::LShr: Opc = X86::SHR32rCL; break;
     case Instruction::AShr: Opc = X86::SAR32rCL; break;
-    case Instruction::Shl:  Opc = X86::SHR32rCL; break;
+    case Instruction::Shl:  Opc = X86::SHL32rCL; break;
     default: return false;
     }
   } else if (I->getType() == Type::Int64Ty) {
     CReg = X86::RCX;
     RC = &X86::GR64RegClass;
     switch (I->getOpcode()) {
-    case Instruction::LShr: Opc = X86::SHL64rCL; break;
+    case Instruction::LShr: Opc = X86::SHR64rCL; break;
     case Instruction::AShr: Opc = X86::SAR64rCL; break;
-    case Instruction::Shl:  Opc = X86::SHR64rCL; break;
+    case Instruction::Shl:  Opc = X86::SHL64rCL; break;
     default: return false;
     }
   } else {
@@ -523,13 +523,13 @@
   unsigned Opc = 0;
   const TargetRegisterClass *RC = NULL;
   if (Ty == Type::Int16Ty) {
-    Opc = X86::CMOVNE16rr;
+    Opc = X86::CMOVE16rr;
     RC = &X86::GR16RegClass;
   } else if (Ty == Type::Int32Ty) {
-    Opc = X86::CMOVNE32rr;
+    Opc = X86::CMOVE32rr;
     RC = &X86::GR32RegClass;
   } else if (Ty == Type::Int64Ty) {
-    Opc = X86::CMOVNE64rr;
+    Opc = X86::CMOVE64rr;
     RC = &X86::GR64RegClass;
   } else {
     return false;