[llvm-commits] [llvm] r55846 - /llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

[Dan Gohman]

Author: djg
Date: Fri Sep  5 13:44:22 2008
New Revision: 55846

URL: http://llvm.org/viewvc/llvm-project?rev=55846&view=rev
Log:
FastISel support for AND and OR with type i1.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55846&r1=55845&r2=55846&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Fri Sep  5 13:44:22 2008
@@ -103,12 +103,20 @@
   if (VT == MVT::Other || !VT.isSimple())
     // Unhandled type. Halt "fast" selection and bail.
     return false;
+
   // We only handle legal types. For example, on x86-32 the instruction
   // selector contains all of the 64-bit instructions from x86-64,
   // under the assumption that i64 won't be used if the target doesn't
   // support it.
-  if (!TLI.isTypeLegal(VT))
-    return false;
+  if (!TLI.isTypeLegal(VT)) {
+    // MVT::i1 is special. Allow AND and OR (but not XOR) because they
+    // don't require additional zeroing, which makes them easy.
+    if (VT == MVT::i1 &&
+        (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR))
+      VT = TLI.getTypeToTransformTo(VT);
+    else
+      return false;
+  }
 
   unsigned Op0 = getRegForValue(I->getOperand(0));
   if (Op0 == 0)