[llvm-commits] [llvm] r55643 - /llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
Dale Johannesen
dalej at apple.com
Tue Sep 2 13:30:24 PDT 2008
Author: johannes
Date: Tue Sep 2 15:30:23 2008
New Revision: 55643
URL: http://llvm.org/viewvc/llvm-project?rev=55643&view=rev
Log:
Fix some bugs in the code sequences for atomics.
Modified:
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=55643&r1=55642&r2=55643&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Tue Sep 2 15:30:23 2008
@@ -3881,8 +3881,8 @@
MachineRegisterInfo &RegInfo = F->getRegInfo();
unsigned TmpReg = (!BinOpcode) ? incr :
RegInfo.createVirtualRegister(
- is64bit ? (const TargetRegisterClass *) &PPC::GPRCRegClass :
- (const TargetRegisterClass *) &PPC::G8RCRegClass);
+ is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
+ (const TargetRegisterClass *) &PPC::GPRCRegClass);
// thisMBB:
// ...
@@ -3944,8 +3944,8 @@
MachineRegisterInfo &RegInfo = F->getRegInfo();
const TargetRegisterClass *RC =
- is64bit ? (const TargetRegisterClass *) &PPC::GPRCRegClass :
- (const TargetRegisterClass *) &PPC::G8RCRegClass;
+ is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
+ (const TargetRegisterClass *) &PPC::GPRCRegClass;
unsigned PtrReg = RegInfo.createVirtualRegister(RC);
unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
@@ -3969,7 +3969,7 @@
// anywhere in the word. Hence all this nasty bookkeeping code.
// add ptr1, ptrA, ptrB [copy if ptrA==0]
// rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
- // xor shift, shift1, 24 [16]
+ // xori shift, shift1, 24 [16]
// rlwinm ptr, ptr1, 0, 0, 29
// slw incr2, incr, shift
// li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
@@ -3994,7 +3994,7 @@
}
BuildMI(BB, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
.addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
- BuildMI(BB, TII->get(is64bit ? PPC::XOR8 : PPC::XOR), ShiftReg)
+ BuildMI(BB, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
.addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
if (is64bit)
BuildMI(BB, TII->get(PPC::RLDICR), PtrReg)
@@ -4251,8 +4251,8 @@
MachineRegisterInfo &RegInfo = F->getRegInfo();
const TargetRegisterClass *RC =
- is64bit ? (const TargetRegisterClass *) &PPC::GPRCRegClass :
- (const TargetRegisterClass *) &PPC::G8RCRegClass;
+ is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
+ (const TargetRegisterClass *) &PPC::GPRCRegClass;
unsigned PtrReg = RegInfo.createVirtualRegister(RC);
unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
@@ -4277,7 +4277,7 @@
// anywhere in the word. Hence all this nasty bookkeeping code.
// add ptr1, ptrA, ptrB [copy if ptrA==0]
// rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
- // xor shift, shift1, 24 [16]
+ // xori shift, shift1, 24 [16]
// rlwinm ptr, ptr1, 0, 0, 29
// slw newval2, newval, shift
// slw oldval2, oldval,shift
@@ -4309,7 +4309,7 @@
}
BuildMI(BB, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
.addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
- BuildMI(BB, TII->get(is64bit ? PPC::XOR8 : PPC::XOR), ShiftReg)
+ BuildMI(BB, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
.addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
if (is64bit)
BuildMI(BB, TII->get(PPC::RLDICR), PtrReg)
More information about the llvm-commits
mailing list