[llvm-commits] [llvm] r55598 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrInfo.td
Evan Cheng
evan.cheng at apple.com
Mon Sep 1 00:34:13 PDT 2008
Author: evancheng
Date: Mon Sep 1 02:34:13 2008
New Revision: 55598
URL: http://llvm.org/viewvc/llvm-project?rev=55598&view=rev
Log:
AXI2 and AXI3 instruction encodings.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=55598&r1=55597&r2=55598&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Sep 1 02:34:13 2008
@@ -191,6 +191,15 @@
let Inst{22} = 0; // B bit
let Inst{24} = 1; // P bit
}
+class AXI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+ list<dag> pattern>
+ : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
+ "", pattern> {
+ let Inst{20} = 1; // L bit
+ let Inst{21} = 0; // W bit
+ let Inst{22} = 0; // B bit
+ let Inst{24} = 1; // P bit
+}
class AI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: AI2<opcod, oops, iops, f, opc, asm, pattern> {
@@ -199,6 +208,15 @@
let Inst{22} = 1; // B bit
let Inst{24} = 1; // P bit
}
+class AXI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+ list<dag> pattern>
+ : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
+ "", pattern> {
+ let Inst{20} = 1; // L bit
+ let Inst{21} = 0; // W bit
+ let Inst{22} = 1; // B bit
+ let Inst{24} = 1; // P bit
+}
// stores
class AI2stw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
@@ -209,6 +227,15 @@
let Inst{22} = 0; // B bit
let Inst{24} = 1; // P bit
}
+class AXI2stw<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+ list<dag> pattern>
+ : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
+ "", pattern> {
+ let Inst{20} = 0; // L bit
+ let Inst{21} = 0; // W bit
+ let Inst{22} = 0; // B bit
+ let Inst{24} = 1; // P bit
+}
class AI2stb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: AI2<opcod, oops, iops, f, opc, asm, pattern> {
@@ -217,6 +244,15 @@
let Inst{22} = 1; // B bit
let Inst{24} = 1; // P bit
}
+class AXI2stb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+ list<dag> pattern>
+ : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
+ "", pattern> {
+ let Inst{20} = 0; // L bit
+ let Inst{21} = 0; // W bit
+ let Inst{22} = 1; // B bit
+ let Inst{24} = 1; // P bit
+}
// Pre-indexed loads
class AI2ldwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
@@ -321,6 +357,18 @@
let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit
}
+class AXI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+ list<dag> pattern>
+ : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
+ "", pattern> {
+ let Inst{4} = 1;
+ let Inst{5} = 1; // H bit
+ let Inst{6} = 0; // S bit
+ let Inst{7} = 1;
+ let Inst{20} = 1; // L bit
+ let Inst{21} = 0; // W bit
+ let Inst{24} = 1; // P bit
+}
class AI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
@@ -333,6 +381,18 @@
let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit
}
+class AXI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+ list<dag> pattern>
+ : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
+ "", pattern> {
+ let Inst{4} = 1;
+ let Inst{5} = 1; // H bit
+ let Inst{6} = 1; // S bit
+ let Inst{7} = 1;
+ let Inst{20} = 1; // L bit
+ let Inst{21} = 0; // W bit
+ let Inst{24} = 1; // P bit
+}
class AI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
@@ -345,6 +405,18 @@
let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit
}
+class AXI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+ list<dag> pattern>
+ : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
+ "", pattern> {
+ let Inst{4} = 1;
+ let Inst{5} = 0; // H bit
+ let Inst{6} = 1; // S bit
+ let Inst{7} = 1;
+ let Inst{20} = 1; // L bit
+ let Inst{21} = 0; // W bit
+ let Inst{24} = 1; // P bit
+}
class AI3ldd<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
@@ -371,6 +443,18 @@
let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit
}
+class AXI3sth<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+ list<dag> pattern>
+ : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
+ "", pattern> {
+ let Inst{4} = 1;
+ let Inst{5} = 1; // H bit
+ let Inst{6} = 0; // S bit
+ let Inst{7} = 1;
+ let Inst{20} = 0; // L bit
+ let Inst{21} = 0; // W bit
+ let Inst{24} = 1; // P bit
+}
class AI3std<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=55598&r1=55597&r2=55598&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Sep 1 02:34:13 2008
@@ -469,44 +469,44 @@
let AddedComplexity = 10 in {
let isSimpleLoad = 1 in
-def PICLD : AXI2<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
+def PICLD : AXI2ldw<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, "${addr:label}:\n\tldr$p $dst, $addr",
[(set GPR:$dst, (load addrmodepc:$addr))]>;
-def PICLDZH : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
+def PICLDZH : AXI3ldh<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr",
[(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
-def PICLDZB : AXI2<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
+def PICLDZB : AXI2ldb<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr",
[(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
-def PICLDH : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
+def PICLDH : AXI3ldh<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr",
[(set GPR:$dst, (extloadi16 addrmodepc:$addr))]>;
-def PICLDB : AXI2<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
+def PICLDB : AXI2ldb<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr",
[(set GPR:$dst, (extloadi8 addrmodepc:$addr))]>;
-def PICLDSH : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
+def PICLDSH : AXI3ldsh<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, "${addr:label}:\n\tldr${p}sh $dst, $addr",
[(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
-def PICLDSB : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
+def PICLDSB : AXI3ldsb<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, "${addr:label}:\n\tldr${p}sb $dst, $addr",
[(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
}
let AddedComplexity = 10 in {
-def PICSTR : AXI2<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
+def PICSTR : AXI2stw<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
Pseudo, "${addr:label}:\n\tstr$p $src, $addr",
[(store GPR:$src, addrmodepc:$addr)]>;
-def PICSTRH : AXI3<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
+def PICSTRH : AXI3sth<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
Pseudo, "${addr:label}:\n\tstr${p}h $src, $addr",
[(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
-def PICSTRB : AXI2<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
+def PICSTRB : AXI2stb<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
Pseudo, "${addr:label}:\n\tstr${p}b $src, $addr",
[(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
}
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