[llvm-commits] [llvm] r55504 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/IA64/ lib/Target/Mips/ lib/Target/PIC16/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ utils/TableGen/
Evan Cheng
evan.cheng at apple.com
Fri Aug 29 15:19:55 PDT 2008
Actually I decided I didn't need to back out your patch after all. I
will fix DAG combiner only. Thanks.
Evan
On Aug 29, 2008, at 3:07 PM, Evan Cheng wrote:
> Hi Gabor,
>
> I am forced to back out this patch. I think it's fine but I can't
> cleanly back out 55498 without backing this out as well. Sorry about
> it. Can you re-commit the patch after getting DAG combiner to build
> again?
>
> Thanks,
>
> Evan
>
> On Aug 28, 2008, at 2:40 PM, Gabor Greif wrote:
>
>> Author: ggreif
>> Date: Thu Aug 28 16:40:38 2008
>> New Revision: 55504
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=55504&view=rev
>> Log:
>> erect abstraction boundaries for accessing SDValue members, rename
>> Val -> Node to reflect semantics
>>
>> Modified:
>> llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h
>> llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
>> llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
>> llvm/trunk/include/llvm/Target/TargetLowering.h
>> llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
>> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
>> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
>> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
>> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
>> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
>> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
>> llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
>> llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
>> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
>> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
>> llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
>> llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
>> llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>> llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
>> llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
>> llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
>> llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
>> llvm/trunk/lib/Target/CellSPU/SPUOperands.td
>> llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp
>> llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp
>> llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
>> llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
>> llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
>> llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
>> llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
>> llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
>> llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td
>> llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp
>> llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
>> llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
>> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>> llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
>>
>> Modified: llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h (original)
>> +++ llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h Thu Aug 28
>> 16:40:38 2008
>> @@ -37,7 +37,7 @@
>> else if (Chain->getNumOperands() > 0) {
>> SDValue C0 = Chain->getOperand(0);
>> if (C0.getValueType() == MVT::Other)
>> - return C0.Val != Op && IsChainCompatible(C0.Val, Op);
>> + return C0.getNode() != Op && IsChainCompatible(C0.getNode(),
>> Op);
>> }
>> return true;
>> }
>> @@ -76,9 +76,9 @@
>> /// AddToISelQueue - adds a node to the instruction
>> /// selection queue.
>> void AddToISelQueue(SDValue N) DISABLE_INLINE {
>> - int Id = N.Val->getNodeId();
>> + int Id = N.getNode()->getNodeId();
>> if (Id != -1 && !isQueued(Id)) {
>> - ISelQueue.push_back(N.Val);
>> + ISelQueue.push_back(N.getNode());
>> std::push_heap(ISelQueue.begin(), ISelQueue.end(), isel_sort());
>> setQueued(Id);
>> }
>> @@ -120,7 +120,7 @@
>> void ReplaceUses(SDValue F, SDValue T) DISABLE_INLINE {
>> ISelQueueUpdater ISQU(ISelQueue);
>> CurDAG->ReplaceAllUsesOfValueWith(F, T, &ISQU);
>> - setSelected(F.Val->getNodeId());
>> + setSelected(F.getNode()->getNodeId());
>> UpdateQueue(ISQU);
>> }
>>
>> @@ -131,7 +131,7 @@
>> ISelQueueUpdater ISQU(ISelQueue);
>> CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num, &ISQU);
>> for (unsigned i = 0; i != Num; ++i)
>> - setSelected(F[i].Val->getNodeId());
>> + setSelected(F[i].getNode()->getNodeId());
>> UpdateQueue(ISQU);
>> }
>>
>> @@ -165,7 +165,7 @@
>> // a reference to the root node, preventing it from being deleted,
>> // and tracking any changes of the root.
>> HandleSDNode Dummy(CurDAG->getRoot());
>> - ISelQueue.push_back(CurDAG->getRoot().Val);
>> + ISelQueue.push_back(CurDAG->getRoot().getNode());
>>
>> // Select pending nodes from the instruction selection queue
>> // until no more nodes are left for selection.
>>
>> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
>> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Thu Aug 28
>> 16:40:38 2008
>> @@ -170,7 +170,7 @@
>> /// setRoot - Set the current root tag of the SelectionDAG.
>> ///
>> const SDValue &setRoot(SDValue N) {
>> - assert((!N.Val || N.getValueType() == MVT::Other) &&
>> + assert((!N.getNode() || N.getValueType() == MVT::Other) &&
>> "DAG root value is not a chain!");
>> return Root = N;
>> }
>> @@ -295,7 +295,7 @@
>> SDValue Flag) {
>> const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
>> SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N,
>> Flag };
>> - return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.Val ? 4 : 3);
>> + return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.getNode() ?
>> 4 : 3);
>> }
>>
>> // Similar to last getCopyToReg() except parameter Reg is a SDValue
>> @@ -303,7 +303,7 @@
>> SDValue Flag) {
>> const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
>> SDValue Ops[] = { Chain, Reg, N, Flag };
>> - return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.Val ? 4 : 3);
>> + return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.getNode() ?
>> 4 : 3);
>> }
>>
>> SDValue getCopyFromReg(SDValue Chain, unsigned Reg, MVT VT) {
>> @@ -319,7 +319,7 @@
>> SDValue Flag) {
>> const MVT *VTs = getNodeValueTypes(VT, MVT::Other, MVT::Flag);
>> SDValue Ops[] = { Chain, getRegister(Reg, VT), Flag };
>> - return getNode(ISD::CopyFromReg, VTs, 3, Ops, Flag.Val ? 3 : 2);
>> + return getNode(ISD::CopyFromReg, VTs, 3, Ops, Flag.getNode() ?
>> 3 : 2);
>> }
>>
>> SDValue getCondCode(ISD::CondCode Cond);
>> @@ -347,7 +347,7 @@
>> Ops.push_back(Op2);
>> Ops.push_back(InFlag);
>> return getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0],
>> - (unsigned)Ops.size() - (InFlag.Val == 0 ? 1 :
>> 0));
>> + (unsigned)Ops.size() - (InFlag.getNode() == 0 ?
>> 1 : 0));
>> }
>>
>> /// getNode - Gets or creates the specified node.
>>
>> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
>> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Thu Aug 28
>> 16:40:38 2008
>> @@ -837,29 +837,33 @@
>> /// of information is represented with the SDValue value type.
>> ///
>> class SDValue {
>> -public:
>> - SDNode *Val; // The node defining the value we are using.
>> -private:
>> + SDNode *Node; // The node defining the value we are using.
>> unsigned ResNo; // Which return value of the node we are using.
>> public:
>> - SDValue() : Val(0), ResNo(0) {}
>> - SDValue(SDNode *val, unsigned resno) : Val(val), ResNo(resno) {}
>> + SDValue() : Node(0), ResNo(0) {}
>> + SDValue(SDNode *node, unsigned resno) : Node(node), ResNo(resno)
>> {}
>>
>> /// get the index which selects a specific result in the SDNode
>> unsigned getResNo() const { return ResNo; }
>>
>> + /// get the SDNode which holds the desired result
>> + SDNode *getNode() const { return Node; }
>> +
>> + /// set the SDNode
>> + void setNode(SDNode *N) { Node = N; }
>> +
>> bool operator==(const SDValue &O) const {
>> - return Val == O.Val && ResNo == O.ResNo;
>> + return Node == O.Node && ResNo == O.ResNo;
>> }
>> bool operator!=(const SDValue &O) const {
>> return !operator==(O);
>> }
>> bool operator<(const SDValue &O) const {
>> - return Val < O.Val || (Val == O.Val && ResNo < O.ResNo);
>> + return Node < O.Node || (Node == O.Node && ResNo < O.ResNo);
>> }
>>
>> SDValue getValue(unsigned R) const {
>> - return SDValue(Val, R);
>> + return SDValue(Node, R);
>> }
>>
>> // isOperandOf - Return true if this node is an operand of N.
>> @@ -894,12 +898,12 @@
>> unsigned Depth = 2) const;
>>
>> /// use_empty - Return true if there are no nodes using value ResNo
>> - /// of node Val.
>> + /// of Node.
>> ///
>> inline bool use_empty() const;
>>
>> /// hasOneUse - Return true if there is exactly one node using value
>> - /// ResNo of node Val.
>> + /// ResNo of Node.
>> ///
>> inline bool hasOneUse() const;
>> };
>> @@ -913,8 +917,8 @@
>> return SDValue((SDNode*)-1, 0);
>> }
>> static unsigned getHashValue(const SDValue &Val) {
>> - return ((unsigned)((uintptr_t)Val.Val >> 4) ^
>> - (unsigned)((uintptr_t)Val.Val >> 9)) + Val.getResNo();
>> + return ((unsigned)((uintptr_t)Val.getNode() >> 4) ^
>> + (unsigned)((uintptr_t)Val.getNode() >> 9)) +
>> Val.getResNo();
>> }
>> static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
>> return LHS == RHS;
>> @@ -927,13 +931,13 @@
>> template<> struct simplify_type<SDValue> {
>> typedef SDNode* SimpleType;
>> static SimpleType getSimplifiedValue(const SDValue &Val) {
>> - return static_cast<SimpleType>(Val.Val);
>> + return static_cast<SimpleType>(Val.getNode());
>> }
>> };
>> template<> struct simplify_type<const SDValue> {
>> typedef SDNode* SimpleType;
>> static SimpleType getSimplifiedValue(const SDValue &Val) {
>> - return static_cast<SimpleType>(Val.Val);
>> + return static_cast<SimpleType>(Val.getNode());
>> }
>> };
>>
>> @@ -977,8 +981,9 @@
>>
>> const SDValue& getSDValue() const { return Operand; }
>>
>> - SDNode *&getVal() { return Operand.Val; }
>> - SDNode *const &getVal() const { return Operand.Val; }
>> + SDValue &getSDValue() { return Operand; }
>> + SDNode *getVal() { return Operand.getNode(); }
>> + SDNode *getVal() const { return Operand.getNode(); } // FIXME:
>> const correct?
>>
>> bool operator==(const SDValue &O) const {
>> return Operand == O;
>> @@ -1323,7 +1328,7 @@
>> for (unsigned i = 0; i != NumOps; ++i) {
>> OperandList[i] = Ops[i];
>> OperandList[i].setUser(this);
>> - Ops[i].Val->addUse(OperandList[i]);
>> + Ops[i].getNode()->addUse(OperandList[i]);
>> }
>>
>> ValueList = VTs.VTs;
>> @@ -1393,34 +1398,34 @@
>> // Define inline functions from the SDValue class.
>>
>> inline unsigned SDValue::getOpcode() const {
>> - return Val->getOpcode();
>> + return Node->getOpcode();
>> }
>> inline MVT SDValue::getValueType() const {
>> - return Val->getValueType(ResNo);
>> + return Node->getValueType(ResNo);
>> }
>> inline unsigned SDValue::getNumOperands() const {
>> - return Val->getNumOperands();
>> + return Node->getNumOperands();
>> }
>> inline const SDValue &SDValue::getOperand(unsigned i) const {
>> - return Val->getOperand(i);
>> + return Node->getOperand(i);
>> }
>> inline uint64_t SDValue::getConstantOperandVal(unsigned i) const {
>> - return Val->getConstantOperandVal(i);
>> + return Node->getConstantOperandVal(i);
>> }
>> inline bool SDValue::isTargetOpcode() const {
>> - return Val->isTargetOpcode();
>> + return Node->isTargetOpcode();
>> }
>> inline bool SDValue::isMachineOpcode() const {
>> - return Val->isMachineOpcode();
>> + return Node->isMachineOpcode();
>> }
>> inline unsigned SDValue::getMachineOpcode() const {
>> - return Val->getMachineOpcode();
>> + return Node->getMachineOpcode();
>> }
>> inline bool SDValue::use_empty() const {
>> - return !Val->hasAnyUseOfValue(ResNo);
>> + return !Node->hasAnyUseOfValue(ResNo);
>> }
>> inline bool SDValue::hasOneUse() const {
>> - return Val->hasNUsesOfValue(1, ResNo);
>> + return Node->hasNUsesOfValue(1, ResNo);
>> }
>>
>> /// UnarySDNode - This class is used for single-operand SDNodes.
>> This is solely
>> @@ -2321,7 +2326,7 @@
>> }
>>
>> pointer operator*() const {
>> - return Node->getOperand(Operand).Val;
>> + return Node->getOperand(Operand).getNode();
>> }
>> pointer operator->() const { return operator*(); }
>>
>>
>> Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
>> +++ llvm/trunk/include/llvm/Target/TargetLowering.h Thu Aug 28
>> 16:40:38 2008
>> @@ -1086,11 +1086,11 @@
>> static bool CheckTailCallReturnConstraints(SDValue Call, SDValue
>> Ret) {
>> unsigned NumOps = Ret.getNumOperands();
>> if ((NumOps == 1 &&
>> - (Ret.getOperand(0) == SDValue(Call.Val,1) ||
>> - Ret.getOperand(0) == SDValue(Call.Val,0))) ||
>> + (Ret.getOperand(0) == SDValue(Call.getNode(),1) ||
>> + Ret.getOperand(0) == SDValue(Call.getNode(),0))) ||
>> (NumOps > 1 &&
>> - Ret.getOperand(0) == SDValue(Call.Val,Call.Val-
>>> getNumValues()-1) &&
>> - Ret.getOperand(1) == SDValue(Call.Val,0)))
>> + Ret.getOperand(0) == SDValue(Call.getNode(),Call.getNode()-
>>> getNumValues()-1) &&
>> + Ret.getOperand(1) == SDValue(Call.getNode(),0)))
>> return true;
>> return false;
>> }
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -148,8 +148,8 @@
>> // Visitation implementation - Implement dag node combining for
>> different
>> // node types. The semantics are as follows:
>> // Return Value:
>> - // SDValue.Val == 0 - No change was made
>> - // SDValue.Val == N - N was replaced, is dead, and is
>> already handled.
>> + // SDValue.getNode() == 0 - No change was made
>> + // SDValue.getNode() == N - N was replaced, is dead, and is
>> already handled.
>> // otherwise - N should be replaced by the returned
>> Operand.
>> //
>> SDValue visitTokenFactor(SDNode *N);
>> @@ -491,7 +491,7 @@
>> // free when it is profitable to do so.
>> static bool isOneUseSetCC(SDValue N) {
>> SDValue N0, N1, N2;
>> - if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
>> + if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
>> return true;
>> return false;
>> }
>> @@ -503,11 +503,11 @@
>> if (N0.getOpcode() == Opc &&
>> isa<ConstantSDNode>(N0.getOperand(1))) {
>> if (isa<ConstantSDNode>(N1)) {
>> SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
>> - AddToWorkList(OpNode.Val);
>> + AddToWorkList(OpNode.getNode());
>> return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
>> } else if (N0.hasOneUse()) {
>> SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
>> - AddToWorkList(OpNode.Val);
>> + AddToWorkList(OpNode.getNode());
>> return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
>> }
>> }
>> @@ -516,11 +516,11 @@
>> if (N1.getOpcode() == Opc &&
>> isa<ConstantSDNode>(N1.getOperand(1))) {
>> if (isa<ConstantSDNode>(N0)) {
>> SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
>> - AddToWorkList(OpNode.Val);
>> + AddToWorkList(OpNode.getNode());
>> return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
>> } else if (N1.hasOneUse()) {
>> SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
>> - AddToWorkList(OpNode.Val);
>> + AddToWorkList(OpNode.getNode());
>> return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
>> }
>> }
>> @@ -532,7 +532,7 @@
>> assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
>> ++NodesCombined;
>> DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
>> - DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG));
>> + DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG));
>> DOUT << " and " << NumTo-1 << " other values\n";
>> WorkListRemover DeadNodes(*this);
>> DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
>> @@ -540,8 +540,8 @@
>> if (AddTo) {
>> // Push the new nodes and any users onto the worklist
>> for (unsigned i = 0, e = NumTo; i != e; ++i) {
>> - AddToWorkList(To[i].Val);
>> - AddUsersToWorkList(To[i].Val);
>> + AddToWorkList(To[i].getNode());
>> + AddUsersToWorkList(To[i].getNode());
>> }
>> }
>>
>> @@ -564,12 +564,12 @@
>> return false;
>>
>> // Revisit the node.
>> - AddToWorkList(Op.Val);
>> + AddToWorkList(Op.getNode());
>>
>> // Replace the old value with the new one.
>> ++NodesCombined;
>> - DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG));
>> - DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG));
>> + DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG));
>> + DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG));
>> DOUT << '\n';
>>
>> // Replace all uses. If any nodes become isomorphic to other
>> nodes and
>> @@ -578,22 +578,22 @@
>> DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
>>
>> // Push the new node and any (possibly new) users onto the worklist.
>> - AddToWorkList(TLO.New.Val);
>> - AddUsersToWorkList(TLO.New.Val);
>> + AddToWorkList(TLO.New.getNode());
>> + AddUsersToWorkList(TLO.New.getNode());
>>
>> // Finally, if the node is now dead, remove it from the graph.
>> The node
>> // may not be dead if the replacement process recursively
>> simplified to
>> // something else needing this node.
>> - if (TLO.Old.Val->use_empty()) {
>> - removeFromWorkList(TLO.Old.Val);
>> + if (TLO.Old.getNode()->use_empty()) {
>> + removeFromWorkList(TLO.Old.getNode());
>>
>> // If the operands of this node are only used by the node, they
>> will now
>> // be dead. Make sure to visit them first to delete dead nodes
>> early.
>> - for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e;
>> ++i)
>> - if (TLO.Old.Val->getOperand(i).Val->hasOneUse())
>> - AddToWorkList(TLO.Old.Val->getOperand(i).Val);
>> + for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands();
>> i != e; ++i)
>> + if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
>> + AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
>>
>> - DAG.DeleteNode(TLO.Old.Val);
>> + DAG.DeleteNode(TLO.Old.getNode());
>> }
>> return true;
>> }
>> @@ -608,7 +608,7 @@
>> // reduced number of uses, allowing other xforms.
>> if (N->use_empty() && N != &Dummy) {
>> for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
>> - AddToWorkList(N->getOperand(i).Val);
>> + AddToWorkList(N->getOperand(i).getNode());
>>
>> DAG.DeleteNode(N);
>> return;
>> @@ -616,7 +616,7 @@
>>
>> SDValue RV = combine(N);
>>
>> - if (RV.Val == 0)
>> + if (RV.getNode() == 0)
>> return;
>>
>> ++NodesCombined;
>> @@ -625,19 +625,19 @@
>> // zero, we know that the node must have defined multiple values and
>> // CombineTo was used. Since CombineTo takes care of the worklist
>> // mechanics for us, we have no work to do in this case.
>> - if (RV.Val == N)
>> + if (RV.getNode() == N)
>> return;
>>
>> assert(N->getOpcode() != ISD::DELETED_NODE &&
>> - RV.Val->getOpcode() != ISD::DELETED_NODE &&
>> + RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
>> "Node was deleted but visit returned new node!");
>>
>> DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
>> - DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
>> + DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG));
>> DOUT << '\n';
>>
>> - if (N->getNumValues() == RV.Val->getNumValues())
>> - DAG.ReplaceAllUsesWith(N, RV.Val);
>> + if (N->getNumValues() == RV.getNode()->getNumValues())
>> + DAG.ReplaceAllUsesWith(N, RV.getNode());
>> else {
>> assert(N->getValueType(0) == RV.getValueType() &&
>> N->getNumValues() == 1 && "Type mismatch");
>> @@ -650,8 +650,8 @@
>> DAG.DeleteNode(N);
>>
>> // Push the new node and any users onto the worklist
>> - AddToWorkList(RV.Val);
>> - AddUsersToWorkList(RV.Val);
>> + AddToWorkList(RV.getNode());
>> + AddUsersToWorkList(RV.getNode());
>> }
>>
>> void DAGCombiner::Run(bool RunningAfterLegalize) {
>> @@ -761,7 +761,7 @@
>> SDValue RV = visit(N);
>>
>> // If nothing happened, try a target-specific DAG combine.
>> - if (RV.Val == 0) {
>> + if (RV.getNode() == 0) {
>> assert(N->getOpcode() != ISD::DELETED_NODE &&
>> "Node was deleted but visit returned NULL!");
>>
>> @@ -778,7 +778,7 @@
>>
>> // If N is a commutative binary node, try commuting it to enable
>> more
>> // sdisel CSE.
>> - if (RV.Val == 0 &&
>> + if (RV.getNode() == 0 &&
>> SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
>> N->getNumValues() == 1) {
>> SDValue N0 = N->getOperand(0);
>> @@ -815,9 +815,9 @@
>> // If N has two operands, where one has an input chain equal to
>> the other,
>> // the 'other' chain is redundant.
>> if (N->getNumOperands() == 2) {
>> - if (getInputChainForNode(N->getOperand(0).Val) == N-
>>> getOperand(1))
>> + if (getInputChainForNode(N->getOperand(0).getNode()) == N-
>>> getOperand(1))
>> return N->getOperand(0);
>> - if (getInputChainForNode(N->getOperand(1).Val) == N-
>>> getOperand(0))
>> + if (getInputChainForNode(N->getOperand(1).getNode()) == N-
>>> getOperand(0))
>> return N->getOperand(1);
>> }
>>
>> @@ -847,11 +847,11 @@
>>
>> case ISD::TokenFactor:
>> if ((CombinerAA || Op.hasOneUse()) &&
>> - std::find(TFs.begin(), TFs.end(), Op.Val) ==
>> TFs.end()) {
>> + std::find(TFs.begin(), TFs.end(), Op.getNode()) ==
>> TFs.end()) {
>> // Queue up for processing.
>> - TFs.push_back(Op.Val);
>> + TFs.push_back(Op.getNode());
>> // Clean up in case the token factor is removed.
>> - AddToWorkList(Op.Val);
>> + AddToWorkList(Op.getNode());
>> Changed = true;
>> break;
>> }
>> @@ -859,7 +859,7 @@
>>
>> default:
>> // Only add if it isn't already in the list.
>> - if (SeenOps.insert(Op.Val))
>> + if (SeenOps.insert(Op.getNode()))
>> Ops.push_back(Op);
>> else
>> Changed = true;
>> @@ -905,7 +905,7 @@
>> SDValue N00 = N0.getOperand(0);
>> SDValue N01 = N0.getOperand(1);
>> ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
>> - if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() &&
>> + if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()-
>>> hasOneUse() &&
>> isa<ConstantSDNode>(N00.getOperand(1))) {
>> N0 = DAG.getNode(ISD::ADD, VT,
>> DAG.getNode(ISD::SHL, VT, N00.getOperand(0),
>> N01),
>> @@ -975,7 +975,7 @@
>> // fold vector ops
>> if (VT.isVector()) {
>> SDValue FoldedVOp = SimplifyVBinOp(N);
>> - if (FoldedVOp.Val) return FoldedVOp;
>> + if (FoldedVOp.getNode()) return FoldedVOp;
>> }
>>
>> // fold (add x, undef) -> undef
>> @@ -1001,7 +1001,7 @@
>> N0.getOperand(1));
>> // reassociate add
>> SDValue RADD = ReassociateOps(ISD::ADD, N0, N1);
>> - if (RADD.Val != 0)
>> + if (RADD.getNode() != 0)
>> return RADD;
>> // fold ((0-A) + B) -> B-A
>> if (N0.getOpcode() == ISD::SUB &&
>> isa<ConstantSDNode>(N0.getOperand(0)) &&
>> @@ -1036,23 +1036,23 @@
>> }
>>
>> // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2),
>> c1<<c2), )
>> - if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) {
>> + if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
>> SDValue Result = combineShlAddConstant(N0, N1, DAG);
>> - if (Result.Val) return Result;
>> + if (Result.getNode()) return Result;
>> }
>> - if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) {
>> + if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
>> SDValue Result = combineShlAddConstant(N1, N0, DAG);
>> - if (Result.Val) return Result;
>> + if (Result.getNode()) return Result;
>> }
>>
>> // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
>> - if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) {
>> + if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
>> SDValue Result = combineSelectAndUse(N, N0, N1, DAG);
>> - if (Result.Val) return Result;
>> + if (Result.getNode()) return Result;
>> }
>> - if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
>> + if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
>> SDValue Result = combineSelectAndUse(N, N1, N0, DAG);
>> - if (Result.Val) return Result;
>> + if (Result.getNode()) return Result;
>> }
>>
>> return SDValue();
>> @@ -1121,14 +1121,14 @@
>> SDValue DAGCombiner::visitSUB(SDNode *N) {
>> SDValue N0 = N->getOperand(0);
>> SDValue N1 = N->getOperand(1);
>> - ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
>> - ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
>> + ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
>> + ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
>> MVT VT = N0.getValueType();
>>
>> // fold vector ops
>> if (VT.isVector()) {
>> SDValue FoldedVOp = SimplifyVBinOp(N);
>> - if (FoldedVOp.Val) return FoldedVOp;
>> + if (FoldedVOp.getNode()) return FoldedVOp;
>> }
>>
>> // fold (sub x, x) -> 0
>> @@ -1148,9 +1148,9 @@
>> if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
>> return N0.getOperand(0);
>> // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
>> - if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
>> + if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
>> SDValue Result = combineSelectAndUse(N, N1, N0, DAG);
>> - if (Result.Val) return Result;
>> + if (Result.getNode()) return Result;
>> }
>> // If either operand of a sub is undef, the result is undef
>> if (N0.getOpcode() == ISD::UNDEF)
>> @@ -1171,7 +1171,7 @@
>> // fold vector ops
>> if (VT.isVector()) {
>> SDValue FoldedVOp = SimplifyVBinOp(N);
>> - if (FoldedVOp.Val) return FoldedVOp;
>> + if (FoldedVOp.getNode()) return FoldedVOp;
>> }
>>
>> // fold (mul x, undef) -> 0
>> @@ -1208,7 +1208,7 @@
>> if (N1C && N0.getOpcode() == ISD::SHL &&
>> isa<ConstantSDNode>(N0.getOperand(1))) {
>> SDValue C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
>> - AddToWorkList(C3.Val);
>> + AddToWorkList(C3.getNode());
>> return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
>> }
>>
>> @@ -1218,19 +1218,19 @@
>> SDValue Sh(0,0), Y(0,0);
>> // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
>> if (N0.getOpcode() == ISD::SHL &&
>> isa<ConstantSDNode>(N0.getOperand(1)) &&
>> - N0.Val->hasOneUse()) {
>> + N0.getNode()->hasOneUse()) {
>> Sh = N0; Y = N1;
>> } else if (N1.getOpcode() == ISD::SHL &&
>> - isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val-
>>> hasOneUse()) {
>> + isa<ConstantSDNode>(N1.getOperand(1)) &&
>> N1.getNode()->hasOneUse()) {
>> Sh = N1; Y = N0;
>> }
>> - if (Sh.Val) {
>> + if (Sh.getNode()) {
>> SDValue Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
>> return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
>> }
>> }
>> // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
>> - if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
>> + if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()-
>>> hasOneUse() &&
>> isa<ConstantSDNode>(N0.getOperand(1))) {
>> return DAG.getNode(ISD::ADD, VT,
>> DAG.getNode(ISD::MUL, VT, N0.getOperand(0),
>> N1),
>> @@ -1239,7 +1239,7 @@
>>
>> // reassociate mul
>> SDValue RMUL = ReassociateOps(ISD::MUL, N0, N1);
>> - if (RMUL.Val != 0)
>> + if (RMUL.getNode() != 0)
>> return RMUL;
>>
>> return SDValue();
>> @@ -1248,14 +1248,14 @@
>> SDValue DAGCombiner::visitSDIV(SDNode *N) {
>> SDValue N0 = N->getOperand(0);
>> SDValue N1 = N->getOperand(1);
>> - ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
>> - ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
>> + ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
>> + ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
>> MVT VT = N->getValueType(0);
>>
>> // fold vector ops
>> if (VT.isVector()) {
>> SDValue FoldedVOp = SimplifyVBinOp(N);
>> - if (FoldedVOp.Val) return FoldedVOp;
>> + if (FoldedVOp.getNode()) return FoldedVOp;
>> }
>>
>> // fold (sdiv c1, c2) -> c1/c2
>> @@ -1288,21 +1288,21 @@
>> SDValue SGN = DAG.getNode(ISD::SRA, VT, N0,
>> DAG.getConstant(VT.getSizeInBits()-1,
>>
>> TLI.getShiftAmountTy()));
>> - AddToWorkList(SGN.Val);
>> + AddToWorkList(SGN.getNode());
>> // Add (N0 < 0) ? abs2 - 1 : 0;
>> SDValue SRL = DAG.getNode(ISD::SRL, VT, SGN,
>> DAG.getConstant(VT.getSizeInBits()-
>> lg2,
>>
>> TLI.getShiftAmountTy()));
>> SDValue ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
>> - AddToWorkList(SRL.Val);
>> - AddToWorkList(ADD.Val); // Divide by pow2
>> + AddToWorkList(SRL.getNode());
>> + AddToWorkList(ADD.getNode()); // Divide by pow2
>> SDValue SRA = DAG.getNode(ISD::SRA, VT, ADD,
>> DAG.getConstant(lg2,
>> TLI.getShiftAmountTy()));
>> // If we're dividing by a positive value, we're done.
>> Otherwise, we must
>> // negate the result.
>> if (pow2 > 0)
>> return SRA;
>> - AddToWorkList(SRA.Val);
>> + AddToWorkList(SRA.getNode());
>> return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
>> }
>> // if integer divide is expensive and we satisfy the requirements,
>> emit an
>> @@ -1310,7 +1310,7 @@
>> if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended()
>>> 1) &&
>> !TLI.isIntDivCheap()) {
>> SDValue Op = BuildSDIV(N);
>> - if (Op.Val) return Op;
>> + if (Op.getNode()) return Op;
>> }
>>
>> // undef / X -> 0
>> @@ -1326,14 +1326,14 @@
>> SDValue DAGCombiner::visitUDIV(SDNode *N) {
>> SDValue N0 = N->getOperand(0);
>> SDValue N1 = N->getOperand(1);
>> - ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
>> - ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
>> + ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
>> + ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
>> MVT VT = N->getValueType(0);
>>
>> // fold vector ops
>> if (VT.isVector()) {
>> SDValue FoldedVOp = SimplifyVBinOp(N);
>> - if (FoldedVOp.Val) return FoldedVOp;
>> + if (FoldedVOp.getNode()) return FoldedVOp;
>> }
>>
>> // fold (udiv c1, c2) -> c1/c2
>> @@ -1353,7 +1353,7 @@
>> DAG.getConstant(SHC-
>>> getAPIntValue()
>> .logBase2
>> (),
>> ADDVT));
>> - AddToWorkList(Add.Val);
>> + AddToWorkList(Add.getNode());
>> return DAG.getNode(ISD::SRL, VT, N0, Add);
>> }
>> }
>> @@ -1361,7 +1361,7 @@
>> // fold (udiv x, c) -> alternate
>> if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
>> SDValue Op = BuildUDIV(N);
>> - if (Op.Val) return Op;
>> + if (Op.getNode()) return Op;
>> }
>>
>> // undef / X -> 0
>> @@ -1395,12 +1395,12 @@
>> // X%C to the equivalent of X-X/C*C.
>> if (N1C && !N1C->isNullValue()) {
>> SDValue Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
>> - AddToWorkList(Div.Val);
>> - SDValue OptimizedDiv = combine(Div.Val);
>> - if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) {
>> + AddToWorkList(Div.getNode());
>> + SDValue OptimizedDiv = combine(Div.getNode());
>> + if (OptimizedDiv.getNode() && OptimizedDiv.getNode() !=
>> Div.getNode()) {
>> SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
>> SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
>> - AddToWorkList(Mul.Val);
>> + AddToWorkList(Mul.getNode());
>> return Sub;
>> }
>> }
>> @@ -1437,7 +1437,7 @@
>> DAG.getNode(ISD::ADD, VT, N1,
>>
>> DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
>> VT));
>> - AddToWorkList(Add.Val);
>> + AddToWorkList(Add.getNode());
>> return DAG.getNode(ISD::AND, VT, N0, Add);
>> }
>> }
>> @@ -1447,11 +1447,11 @@
>> // X%C to the equivalent of X-X/C*C.
>> if (N1C && !N1C->isNullValue()) {
>> SDValue Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
>> - SDValue OptimizedDiv = combine(Div.Val);
>> - if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) {
>> + SDValue OptimizedDiv = combine(Div.getNode());
>> + if (OptimizedDiv.getNode() && OptimizedDiv.getNode() !=
>> Div.getNode()) {
>> SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
>> SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
>> - AddToWorkList(Mul.Val);
>> + AddToWorkList(Mul.getNode());
>> return Sub;
>> }
>> }
>> @@ -1540,9 +1540,9 @@
>> if (LoExists) {
>> SDValue Lo = DAG.getNode(LoOp, N->getValueType(0),
>> N->op_begin(), N->getNumOperands());
>> - AddToWorkList(Lo.Val);
>> - SDValue LoOpt = combine(Lo.Val);
>> - if (LoOpt.Val && LoOpt.Val != Lo.Val &&
>> + AddToWorkList(Lo.getNode());
>> + SDValue LoOpt = combine(Lo.getNode());
>> + if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
>> (!AfterLegalize ||
>> TLI.isOperationLegal(LoOpt.getOpcode(),
>> LoOpt.getValueType())))
>> return CombineTo(N, LoOpt, LoOpt);
>> @@ -1551,9 +1551,9 @@
>> if (HiExists) {
>> SDValue Hi = DAG.getNode(HiOp, N->getValueType(1),
>> N->op_begin(), N->getNumOperands());
>> - AddToWorkList(Hi.Val);
>> - SDValue HiOpt = combine(Hi.Val);
>> - if (HiOpt.Val && HiOpt != Hi &&
>> + AddToWorkList(Hi.getNode());
>> + SDValue HiOpt = combine(Hi.getNode());
>> + if (HiOpt.getNode() && HiOpt != Hi &&
>> (!AfterLegalize ||
>> TLI.isOperationLegal(HiOpt.getOpcode(),
>> HiOpt.getValueType())))
>> return CombineTo(N, HiOpt, HiOpt);
>> @@ -1563,28 +1563,28 @@
>>
>> SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
>> SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
>> - if (Res.Val) return Res;
>> + if (Res.getNode()) return Res;
>>
>> return SDValue();
>> }
>>
>> SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
>> SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
>> - if (Res.Val) return Res;
>> + if (Res.getNode()) return Res;
>>
>> return SDValue();
>> }
>>
>> SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
>> SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
>> - if (Res.Val) return Res;
>> + if (Res.getNode()) return Res;
>>
>> return SDValue();
>> }
>>
>> SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
>> SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
>> - if (Res.Val) return Res;
>> + if (Res.getNode()) return Res;
>>
>> return SDValue();
>> }
>> @@ -1607,7 +1607,7 @@
>> SDValue ORNode = DAG.getNode(N->getOpcode(),
>> N0.getOperand(0).getValueType(),
>> N0.getOperand(0),
>> N1.getOperand(0));
>> - AddToWorkList(ORNode.Val);
>> + AddToWorkList(ORNode.getNode());
>> return DAG.getNode(N0.getOpcode(), VT, ORNode);
>> }
>>
>> @@ -1621,7 +1621,7 @@
>> SDValue ORNode = DAG.getNode(N->getOpcode(),
>> N0.getOperand(0).getValueType(),
>> N0.getOperand(0),
>> N1.getOperand(0));
>> - AddToWorkList(ORNode.Val);
>> + AddToWorkList(ORNode.getNode());
>> return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
>> }
>>
>> @@ -1640,7 +1640,7 @@
>> // fold vector ops
>> if (VT.isVector()) {
>> SDValue FoldedVOp = SimplifyVBinOp(N);
>> - if (FoldedVOp.Val) return FoldedVOp;
>> + if (FoldedVOp.getNode()) return FoldedVOp;
>> }
>>
>> // fold (and x, undef) -> 0
>> @@ -1661,7 +1661,7 @@
>> return DAG.getConstant(0, VT);
>> // reassociate and
>> SDValue RAND = ReassociateOps(ISD::AND, N0, N1);
>> - if (RAND.Val != 0)
>> + if (RAND.getNode() != 0)
>> return RAND;
>> // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
>> if (N1C && N0.getOpcode() == ISD::OR)
>> @@ -1683,7 +1683,7 @@
>> // We actually want to replace all uses of the any_extend with
>> the
>> // zero_extend, to avoid duplicating things. This will later
>> cause this
>> // AND to be folded.
>> - CombineTo(N0.Val, Zext);
>> + CombineTo(N0.getNode(), Zext);
>> return SDValue(N, 0); // Return N so it doesn't get rechecked!
>> }
>> }
>> @@ -1697,19 +1697,19 @@
>> // fold (X == 0) & (Y == 0) -> (X|Y == 0)
>> if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 ==
>> ISD::SETEQ) {
>> SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL,
>> RL);
>> - AddToWorkList(ORNode.Val);
>> + AddToWorkList(ORNode.getNode());
>> return DAG.getSetCC(VT, ORNode, LR, Op1);
>> }
>> // fold (X == -1) & (Y == -1) -> (X&Y == -1)
>> if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 ==
>> ISD::SETEQ) {
>> SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(),
>> LL, RL);
>> - AddToWorkList(ANDNode.Val);
>> + AddToWorkList(ANDNode.getNode());
>> return DAG.getSetCC(VT, ANDNode, LR, Op1);
>> }
>> // fold (X > -1) & (Y > -1) -> (X|Y > -1)
>> if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 ==
>> ISD::SETGT) {
>> SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL,
>> RL);
>> - AddToWorkList(ORNode.Val);
>> + AddToWorkList(ORNode.getNode());
>> return DAG.getSetCC(VT, ORNode, LR, Op1);
>> }
>> }
>> @@ -1729,7 +1729,7 @@
>> // Simplify: and (op x...), (op y...) -> (op (and x, y))
>> if (N0.getOpcode() == N1.getOpcode()) {
>> SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
>> - if (Tmp.Val) return Tmp;
>> + if (Tmp.getNode()) return Tmp;
>> }
>>
>> // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
>> @@ -1738,7 +1738,7 @@
>> SimplifyDemandedBits(SDValue(N, 0)))
>> return SDValue(N, 0);
>> // fold (zext_inreg (extload x)) -> (zextload x)
>> - if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
>> + if (ISD::isEXTLoad(N0.getNode()) &&
>> ISD::isUNINDEXEDLoad(N0.getNode())) {
>> LoadSDNode *LN0 = cast<LoadSDNode>(N0);
>> MVT EVT = LN0->getMemoryVT();
>> // If we zero all the possible extended bits, then we can turn
>> this into
>> @@ -1754,12 +1754,12 @@
>> LN0->isVolatile(),
>> LN0->getAlignment());
>> AddToWorkList(N);
>> - CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
>> + CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
>> return SDValue(N, 0); // Return N so it doesn't get rechecked!
>> }
>> }
>> // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one
>> use
>> - if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
>> + if (ISD::isSEXTLoad(N0.getNode()) &&
>> ISD::isUNINDEXEDLoad(N0.getNode()) &&
>> N0.hasOneUse()) {
>> LoadSDNode *LN0 = cast<LoadSDNode>(N0);
>> MVT EVT = LN0->getMemoryVT();
>> @@ -1776,7 +1776,7 @@
>> LN0->isVolatile(),
>> LN0->getAlignment());
>> AddToWorkList(N);
>> - CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
>> + CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
>> return SDValue(N, 0); // Return N so it doesn't get rechecked!
>> }
>> }
>> @@ -1813,13 +1813,13 @@
>> DAG.getConstant(PtrOff, PtrType));
>> Alignment = MinAlign(Alignment, PtrOff);
>> }
>> - AddToWorkList(NewPtr.Val);
>> + AddToWorkList(NewPtr.getNode());
>> SDValue Load =
>> DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
>> LN0->getSrcValue(), LN0-
>>> getSrcValueOffset(), EVT,
>> LN0->isVolatile(), Alignment);
>> AddToWorkList(N);
>> - CombineTo(N0.Val, Load, Load.getValue(1));
>> + CombineTo(N0.getNode(), Load, Load.getValue(1));
>> return SDValue(N, 0); // Return N so it doesn't get
>> rechecked!
>> }
>> }
>> @@ -1839,7 +1839,7 @@
>> // fold vector ops
>> if (VT.isVector()) {
>> SDValue FoldedVOp = SimplifyVBinOp(N);
>> - if (FoldedVOp.Val) return FoldedVOp;
>> + if (FoldedVOp.getNode()) return FoldedVOp;
>> }
>>
>> // fold (or x, undef) -> -1
>> @@ -1862,10 +1862,10 @@
>> return N1;
>> // reassociate or
>> SDValue ROR = ReassociateOps(ISD::OR, N0, N1);
>> - if (ROR.Val != 0)
>> + if (ROR.getNode() != 0)
>> return ROR;
>> // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
>> - if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
>> + if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()-
>>> hasOneUse() &&
>> isa<ConstantSDNode>(N0.getOperand(1))) {
>> ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
>> return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT,
>> N0.getOperand(0),
>> @@ -1885,7 +1885,7 @@
>> if (cast<ConstantSDNode>(LR)->isNullValue() &&
>> (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
>> SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL,
>> RL);
>> - AddToWorkList(ORNode.Val);
>> + AddToWorkList(ORNode.getNode());
>> return DAG.getSetCC(VT, ORNode, LR, Op1);
>> }
>> // fold (X != -1) | (Y != -1) -> (X&Y != -1)
>> @@ -1893,7 +1893,7 @@
>> if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
>> (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
>> SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(),
>> LL, RL);
>> - AddToWorkList(ANDNode.Val);
>> + AddToWorkList(ANDNode.getNode());
>> return DAG.getSetCC(VT, ANDNode, LR, Op1);
>> }
>> }
>> @@ -1913,7 +1913,7 @@
>> // Simplify: or (op x...), (op y...) -> (op (or x, y))
>> if (N0.getOpcode() == N1.getOpcode()) {
>> SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
>> - if (Tmp.Val) return Tmp;
>> + if (Tmp.getNode()) return Tmp;
>> }
>>
>> // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
>> @@ -1922,7 +1922,7 @@
>> N0.getOperand(1).getOpcode() == ISD::Constant &&
>> N1.getOperand(1).getOpcode() == ISD::Constant &&
>> // Don't increase # computations.
>> - (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
>> + (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
>> // We can only do this xform if we know that bits from X that
>> are set in C2
>> // but not in C1 are already zero. Likewise for Y.
>> const APInt &LHSMask =
>> @@ -2023,14 +2023,14 @@
>> Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt);
>>
>> // If there is an AND of either shifted operand, apply it to the
>> result.
>> - if (LHSMask.Val || RHSMask.Val) {
>> + if (LHSMask.getNode() || RHSMask.getNode()) {
>> APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
>>
>> - if (LHSMask.Val) {
>> + if (LHSMask.getNode()) {
>> APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
>> Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() |
>> RHSBits;
>> }
>> - if (RHSMask.Val) {
>> + if (RHSMask.getNode()) {
>> APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
>> Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() |
>> LHSBits;
>> }
>> @@ -2038,12 +2038,12 @@
>> Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
>> }
>>
>> - return Rot.Val;
>> + return Rot.getNode();
>> }
>>
>> // If there is a mask here, and we have a variable shift, we can't
>> be sure
>> // that we're masking out the right stuff.
>> - if (LHSMask.Val || RHSMask.Val)
>> + if (LHSMask.getNode() || RHSMask.getNode())
>> return 0;
>>
>> // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
>> @@ -2054,9 +2054,9 @@
>> dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
>> if (SUBC->getAPIntValue() == OpSizeInBits) {
>> if (HasROTL)
>> - return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
>> LHSShiftAmt).Val;
>> + return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
>> LHSShiftAmt).getNode();
>> else
>> - return DAG.getNode(ISD::ROTR, VT, LHSShiftArg,
>> RHSShiftAmt).Val;
>> + return DAG.getNode(ISD::ROTR, VT, LHSShiftArg,
>> RHSShiftAmt).getNode();
>> }
>> }
>> }
>> @@ -2069,9 +2069,9 @@
>> dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
>> if (SUBC->getAPIntValue() == OpSizeInBits) {
>> if (HasROTL)
>> - return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
>> LHSShiftAmt).Val;
>> + return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
>> LHSShiftAmt).getNode();
>> else
>> - return DAG.getNode(ISD::ROTR, VT, LHSShiftArg,
>> RHSShiftAmt).Val;
>> + return DAG.getNode(ISD::ROTR, VT, LHSShiftArg,
>> RHSShiftAmt).getNode();
>> }
>> }
>> }
>> @@ -2094,9 +2094,9 @@
>> if (ConstantSDNode *SUBC =
>> cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
>> if (SUBC->getAPIntValue() == OpSizeInBits) {
>> if (HasROTL)
>> - return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
>> LHSShiftAmt).Val;
>> + return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
>> LHSShiftAmt).getNode();
>> else
>> - return DAG.getNode(ISD::ROTR, VT, LHSShiftArg,
>> RHSShiftAmt).Val;
>> + return DAG.getNode(ISD::ROTR, VT, LHSShiftArg,
>> RHSShiftAmt).getNode();
>> }
>> }
>> } else if (LExtOp0.getOpcode() == ISD::SUB &&
>> @@ -2108,9 +2108,9 @@
>> if (ConstantSDNode *SUBC =
>> cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
>> if (SUBC->getAPIntValue() == OpSizeInBits) {
>> if (HasROTL)
>> - return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
>> RHSShiftAmt).Val;
>> + return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
>> RHSShiftAmt).getNode();
>> else
>> - return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
>> LHSShiftAmt).Val;
>> + return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
>> LHSShiftAmt).getNode();
>> }
>> }
>> }
>> @@ -2131,7 +2131,7 @@
>> // fold vector ops
>> if (VT.isVector()) {
>> SDValue FoldedVOp = SimplifyVBinOp(N);
>> - if (FoldedVOp.Val) return FoldedVOp;
>> + if (FoldedVOp.getNode()) return FoldedVOp;
>> }
>>
>> // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
>> @@ -2153,7 +2153,7 @@
>> return N0;
>> // reassociate xor
>> SDValue RXOR = ReassociateOps(ISD::XOR, N0, N1);
>> - if (RXOR.Val != 0)
>> + if (RXOR.getNode() != 0)
>> return RXOR;
>> // fold !(x cc y) -> (x !cc y)
>> if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS,
>> RHS, CC)) {
>> @@ -2169,11 +2169,11 @@
>> }
>> // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
>> if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() ==
>> ISD::ZERO_EXTEND &&
>> - N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0),
>> LHS, RHS, CC)){
>> + N0.getNode()->hasOneUse() &&
>> isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
>> SDValue V = N0.getOperand(0);
>> V = DAG.getNode(ISD::XOR, V.getValueType(), V,
>> DAG.getConstant(1, V.getValueType()));
>> - AddToWorkList(V.Val);
>> + AddToWorkList(V.getNode());
>> return DAG.getNode(ISD::ZERO_EXTEND, VT, V);
>> }
>>
>> @@ -2185,7 +2185,7 @@
>> unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR :
>> ISD::AND;
>> LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
>> RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
>> - AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
>> + AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
>> return DAG.getNode(NewOpcode, VT, LHS, RHS);
>> }
>> }
>> @@ -2197,7 +2197,7 @@
>> unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR :
>> ISD::AND;
>> LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
>> RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
>> - AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
>> + AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
>> return DAG.getNode(NewOpcode, VT, LHS, RHS);
>> }
>> }
>> @@ -2229,7 +2229,7 @@
>> // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
>> if (N0.getOpcode() == N1.getOpcode()) {
>> SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
>> - if (Tmp.Val) return Tmp;
>> + if (Tmp.getNode()) return Tmp;
>> }
>>
>> // Simplify the expression using non-local knowledge.
>> @@ -2243,7 +2243,7 @@
>> /// visitShiftByConstant - Handle transforms common to the three
>> shifts, when
>> /// the shift amount is a constant.
>> SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
>> - SDNode *LHS = N->getOperand(0).Val;
>> + SDNode *LHS = N->getOperand(0).getNode();
>> if (!LHS->hasOneUse()) return SDValue();
>>
>> // We want to pull some binops through shifts, so that we have
>> (and (shift))
>> @@ -2278,7 +2278,7 @@
>> //
>> //void foo(int *X, int i) { X[i & 1235] = 1; }
>> //int bar(int *X, int i) { return X[i & 255]; }
>> - SDNode *BinOpLHSVal = LHS->getOperand(0).Val;
>> + SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
>> if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
>> BinOpLHSVal->getOpcode() != ISD::SRA &&
>> BinOpLHSVal->getOpcode() != ISD::SRL) ||
>> @@ -2502,7 +2502,7 @@
>> return DAG.getNode(ISD::UNDEF, VT);
>>
>> SDValue SmallShift = DAG.getNode(ISD::SRL, SmallVT,
>> N0.getOperand(0), N1);
>> - AddToWorkList(SmallShift.Val);
>> + AddToWorkList(SmallShift.getNode());
>> return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
>> }
>>
>> @@ -2540,7 +2540,7 @@
>> if (ShAmt) {
>> Op = DAG.getNode(ISD::SRL, VT, Op,
>> DAG.getConstant(ShAmt,
>> TLI.getShiftAmountTy()));
>> - AddToWorkList(Op.Val);
>> + AddToWorkList(Op.getNode());
>> }
>> return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
>> }
>> @@ -2612,7 +2612,7 @@
>> SDValue XORNode = DAG.getNode(ISD::XOR, VT0, N0,
>> DAG.getConstant(1, VT0));
>> if (VT == VT0)
>> return XORNode;
>> - AddToWorkList(XORNode.Val);
>> + AddToWorkList(XORNode.getNode());
>> if (VT.bitsGT(VT0))
>> return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
>> return DAG.getNode(ISD::TRUNCATE, VT, XORNode);
>> @@ -2620,13 +2620,13 @@
>> // fold select C, 0, X -> ~C & X
>> if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
>> SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0,
>> DAG.getConstant(1, VT));
>> - AddToWorkList(XORNode.Val);
>> + AddToWorkList(XORNode.getNode());
>> return DAG.getNode(ISD::AND, VT, XORNode, N2);
>> }
>> // fold select C, X, 1 -> ~C | X
>> if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() ==
>> 1) {
>> SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0,
>> DAG.getConstant(1, VT));
>> - AddToWorkList(XORNode.Val);
>> + AddToWorkList(XORNode.getNode());
>> return DAG.getNode(ISD::OR, VT, XORNode, N1);
>> }
>> // fold select C, X, 0 -> C & X
>> @@ -2673,9 +2673,9 @@
>>
>> // Determine if the condition we're dealing with is constant
>> SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1,
>> CC, false);
>> - if (SCC.Val) AddToWorkList(SCC.Val);
>> + if (SCC.getNode()) AddToWorkList(SCC.getNode());
>>
>> - if (ConstantSDNode *SCCC =
>> dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
>> + if (ConstantSDNode *SCCC =
>> dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
>> if (!SCCC->isNullValue())
>> return N2; // cond always true -> true val
>> else
>> @@ -2683,7 +2683,7 @@
>> }
>>
>> // Fold to a simpler select_cc
>> - if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
>> + if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
>> return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
>> SCC.getOperand(0), SCC.getOperand(1), N2, N3,
>> SCC.getOperand(2));
>> @@ -2711,7 +2711,7 @@
>> TargetLowering &TLI) {
>> bool HasCopyToRegUses = false;
>> bool isTruncFree = TLI.isTruncateFree(N->getValueType(0),
>> N0.getValueType());
>> - for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val-
>>> use_end();
>> + for (SDNode::use_iterator UI = N0.getNode()->use_begin(), UE =
>> N0.getNode()->use_end();
>> UI != UE; ++UI) {
>> SDNode *User = *UI;
>> if (User == N)
>> @@ -2755,7 +2755,7 @@
>> SDNode *User = *UI;
>> for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
>> SDValue UseOp = User->getOperand(i);
>> - if (UseOp.Val == N && UseOp.getResNo() == 0) {
>> + if (UseOp.getNode() == N && UseOp.getResNo() == 0) {
>> BothLiveOut = true;
>> break;
>> }
>> @@ -2785,10 +2785,10 @@
>> if (N0.getOpcode() == ISD::TRUNCATE) {
>> // fold (sext (truncate (load x))) -> (sext (smaller load x))
>> // fold (sext (truncate (srl (load x), c))) -> (sext (smaller
>> load (x+c/n)))
>> - SDValue NarrowLoad = ReduceLoadWidth(N0.Val);
>> - if (NarrowLoad.Val) {
>> - if (NarrowLoad.Val != N0.Val)
>> - CombineTo(N0.Val, NarrowLoad);
>> + SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
>> + if (NarrowLoad.getNode()) {
>> + if (NarrowLoad.getNode() != N0.getNode())
>> + CombineTo(N0.getNode(), NarrowLoad);
>> return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad);
>> }
>>
>> @@ -2830,7 +2830,7 @@
>> }
>>
>> // fold (sext (load x)) -> (sext (truncate (sextload x)))
>> - if (ISD::isNON_EXTLoad(N0.Val) &&
>> + if (ISD::isNON_EXTLoad(N0.getNode()) &&
>> ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
>> TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))) {
>> bool DoXform = true;
>> @@ -2847,7 +2847,7 @@
>> LN0->getAlignment());
>> CombineTo(N, ExtLoad);
>> SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(),
>> ExtLoad);
>> - CombineTo(N0.Val, Trunc, ExtLoad.getValue(1));
>> + CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
>> // Extend SetCC uses if necessary.
>> for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
>> SDNode *SetCC = SetCCs[i];
>> @@ -2869,8 +2869,8 @@
>>
>> // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
>> // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
>> - if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
>> - ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
>> + if ((ISD::isSEXTLoad(N0.getNode()) ||
>> ISD::isEXTLoad(N0.getNode())) &&
>> + ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
>> LoadSDNode *LN0 = cast<LoadSDNode>(N0);
>> MVT EVT = LN0->getMemoryVT();
>> if ((!AfterLegalize && !LN0->isVolatile()) ||
>> @@ -2881,7 +2881,7 @@
>> LN0->isVolatile(),
>> LN0->getAlignment());
>> CombineTo(N, ExtLoad);
>> - CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE,
>> N0.getValueType(), ExtLoad),
>> + CombineTo(N0.getNode(), DAG.getNode(ISD::TRUNCATE,
>> N0.getValueType(), ExtLoad),
>> ExtLoad.getValue(1));
>> return SDValue(N, 0); // Return N so it doesn't get rechecked!
>> }
>> @@ -2893,7 +2893,7 @@
>> SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
>> DAG.getConstant(~0ULL, VT),
>> DAG.getConstant(0, VT),
>> cast<CondCodeSDNode>(N0.getOperand(2))-
>>> get(), true);
>> - if (SCC.Val) return SCC;
>> + if (SCC.getNode()) return SCC;
>> }
>>
>> // fold (sext x) -> (zext x) if the sign bit is known zero.
>> @@ -2919,10 +2919,10 @@
>> // fold (zext (truncate (load x))) -> (zext (smaller load x))
>> // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x
>> +c/n)))
>> if (N0.getOpcode() == ISD::TRUNCATE) {
>> - SDValue NarrowLoad = ReduceLoadWidth(N0.Val);
>> - if (NarrowLoad.Val) {
>> - if (NarrowLoad.Val != N0.Val)
>> - CombineTo(N0.Val, NarrowLoad);
>> + SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
>> + if (NarrowLoad.getNode()) {
>> + if (NarrowLoad.getNode() != N0.getNode())
>> + CombineTo(N0.getNode(), NarrowLoad);
>> return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad);
>> }
>> }
>> @@ -2955,7 +2955,7 @@
>> }
>>
>> // fold (zext (load x)) -> (zext (truncate (zextload x)))
>> - if (ISD::isNON_EXTLoad(N0.Val) &&
>> + if (ISD::isNON_EXTLoad(N0.getNode()) &&
>> ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
>> TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
>> bool DoXform = true;
>> @@ -2972,7 +2972,7 @@
>> LN0->getAlignment());
>> CombineTo(N, ExtLoad);
>> SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(),
>> ExtLoad);
>> - CombineTo(N0.Val, Trunc, ExtLoad.getValue(1));
>> + CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
>> // Extend SetCC uses if necessary.
>> for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
>> SDNode *SetCC = SetCCs[i];
>> @@ -2994,8 +2994,8 @@
>>
>> // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
>> // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
>> - if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
>> - ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
>> + if ((ISD::isZEXTLoad(N0.getNode()) ||
>> ISD::isEXTLoad(N0.getNode())) &&
>> + ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
>> LoadSDNode *LN0 = cast<LoadSDNode>(N0);
>> MVT EVT = LN0->getMemoryVT();
>> if ((!AfterLegalize && !LN0->isVolatile()) ||
>> @@ -3006,7 +3006,7 @@
>> LN0->isVolatile(),
>> LN0->getAlignment());
>> CombineTo(N, ExtLoad);
>> - CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE,
>> N0.getValueType(), ExtLoad),
>> + CombineTo(N0.getNode(), DAG.getNode(ISD::TRUNCATE,
>> N0.getValueType(), ExtLoad),
>> ExtLoad.getValue(1));
>> return SDValue(N, 0); // Return N so it doesn't get rechecked!
>> }
>> @@ -3018,7 +3018,7 @@
>> SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
>> DAG.getConstant(1, VT), DAG.getConstant(0, VT),
>> cast<CondCodeSDNode>(N0.getOperand(2))-
>>> get(), true);
>> - if (SCC.Val) return SCC;
>> + if (SCC.getNode()) return SCC;
>> }
>>
>> return SDValue();
>> @@ -3042,10 +3042,10 @@
>> // fold (aext (truncate (load x))) -> (aext (smaller load x))
>> // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x
>> +c/n)))
>> if (N0.getOpcode() == ISD::TRUNCATE) {
>> - SDValue NarrowLoad = ReduceLoadWidth(N0.Val);
>> - if (NarrowLoad.Val) {
>> - if (NarrowLoad.Val != N0.Val)
>> - CombineTo(N0.Val, NarrowLoad);
>> + SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
>> + if (NarrowLoad.getNode()) {
>> + if (NarrowLoad.getNode() != N0.getNode())
>> + CombineTo(N0.getNode(), NarrowLoad);
>> return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad);
>> }
>> }
>> @@ -3076,7 +3076,7 @@
>> }
>>
>> // fold (aext (load x)) -> (aext (truncate (extload x)))
>> - if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
>> + if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
>> ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
>> TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
>> LoadSDNode *LN0 = cast<LoadSDNode>(N0);
>> @@ -3088,7 +3088,7 @@
>> LN0->getAlignment());
>> CombineTo(N, ExtLoad);
>> // Redirect any chain users to the new load.
>> - DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1),
>> SDValue(ExtLoad.Val, 1));
>> + DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1),
>> SDValue(ExtLoad.getNode(), 1));
>> // If any node needs the original loaded value, recompute it.
>> if (!LN0->use_empty())
>> CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getValueType(),
>> ExtLoad),
>> @@ -3100,7 +3100,7 @@
>> // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
>> // fold (aext ( extload x)) -> (aext (truncate (extload x)))
>> if (N0.getOpcode() == ISD::LOAD &&
>> - !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
>> + !ISD::isNON_EXTLoad(N0.getNode()) &&
>> ISD::isUNINDEXEDLoad(N0.getNode()) &&
>> N0.hasOneUse()) {
>> LoadSDNode *LN0 = cast<LoadSDNode>(N0);
>> MVT EVT = LN0->getMemoryVT();
>> @@ -3111,7 +3111,7 @@
>> LN0->isVolatile(),
>> LN0->getAlignment());
>> CombineTo(N, ExtLoad);
>> - CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(),
>> ExtLoad),
>> + CombineTo(N0.getNode(), DAG.getNode(ISD::TRUNCATE,
>> N0.getValueType(), ExtLoad),
>> ExtLoad.getValue(1));
>> return SDValue(N, 0); // Return N so it doesn't get rechecked!
>> }
>> @@ -3122,7 +3122,7 @@
>> SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
>> DAG.getConstant(1, VT), DAG.getConstant(0, VT),
>> cast<CondCodeSDNode>(N0.getOperand(2))-
>>> get(), true);
>> - if (SCC.Val)
>> + if (SCC.getNode())
>> return SCC;
>> }
>>
>> @@ -3145,14 +3145,14 @@
>> break;
>> case ISD::SRL:
>> // Only look at single-use SRLs.
>> - if (!V.Val->hasOneUse())
>> + if (!V.getNode()->hasOneUse())
>> break;
>> if (ConstantSDNode *RHSC =
>> dyn_cast<ConstantSDNode>(V.getOperand(1))) {
>> // See if we can recursively simplify the LHS.
>> unsigned Amt = RHSC->getValue();
>> APInt NewMask = Mask << Amt;
>> SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
>> - if (SimplifyLHS.Val) {
>> + if (SimplifyLHS.getNode()) {
>> return DAG.getNode(ISD::SRL, V.getValueType(),
>> SimplifyLHS, V.getOperand(1));
>> }
>> @@ -3221,7 +3221,7 @@
>> unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
>> SDValue NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
>> DAG.getConstant(PtrOff, PtrType));
>> - AddToWorkList(NewPtr.Val);
>> + AddToWorkList(NewPtr.getNode());
>> SDValue Load = (ExtType == ISD::NON_EXTLOAD)
>> ? DAG.getLoad(VT, LN0->getChain(), NewPtr,
>> LN0->getSrcValue(), LN0->getSrcValueOffset() +
>> PtrOff,
>> @@ -3234,9 +3234,9 @@
>> WorkListRemover DeadNodes(*this);
>> DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
>> &DeadNodes);
>> - CombineTo(N->getOperand(0).Val, Load);
>> + CombineTo(N->getOperand(0).getNode(), Load);
>> } else
>> - CombineTo(N0.Val, Load, Load.getValue(1));
>> + CombineTo(N0.getNode(), Load, Load.getValue(1));
>> if (ShAmt) {
>> if (Opc == ISD::SIGN_EXTEND_INREG)
>> return DAG.getNode(Opc, VT, Load, N->getOperand(1));
>> @@ -3293,7 +3293,7 @@
>> // fold (sext_in_reg (load x)) -> (smaller sextload x)
>> // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/
>> evtbits))
>> SDValue NarrowLoad = ReduceLoadWidth(N);
>> - if (NarrowLoad.Val)
>> + if (NarrowLoad.getNode())
>> return NarrowLoad;
>>
>> // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
>> @@ -3311,8 +3311,8 @@
>> }
>>
>> // fold (sext_inreg (extload x)) -> (sextload x)
>> - if (ISD::isEXTLoad(N0.Val) &&
>> - ISD::isUNINDEXEDLoad(N0.Val) &&
>> + if (ISD::isEXTLoad(N0.getNode()) &&
>> + ISD::isUNINDEXEDLoad(N0.getNode()) &&
>> EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
>> ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
>> TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
>> @@ -3323,11 +3323,11 @@
>> LN0->isVolatile(),
>> LN0->getAlignment());
>> CombineTo(N, ExtLoad);
>> - CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
>> + CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
>> return SDValue(N, 0); // Return N so it doesn't get rechecked!
>> }
>> // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one
>> use
>> - if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
>> + if (ISD::isZEXTLoad(N0.getNode()) &&
>> ISD::isUNINDEXEDLoad(N0.getNode()) &&
>> N0.hasOneUse() &&
>> EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
>> ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
>> @@ -3339,7 +3339,7 @@
>> LN0->isVolatile(),
>> LN0->getAlignment());
>> CombineTo(N, ExtLoad);
>> - CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
>> + CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
>> return SDValue(N, 0); // Return N so it doesn't get rechecked!
>> }
>> return SDValue();
>> @@ -3379,7 +3379,7 @@
>> SDValue Shorter =
>> GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
>> VT.getSizeInBits()));
>> - if (Shorter.Val)
>> + if (Shorter.getNode())
>> return DAG.getNode(ISD::TRUNCATE, VT, Shorter);
>>
>> // fold (truncate (load x)) -> (smaller load x)
>> @@ -3390,8 +3390,8 @@
>> static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
>> SDValue Elt = N->getOperand(i);
>> if (Elt.getOpcode() != ISD::MERGE_VALUES)
>> - return Elt.Val;
>> - return Elt.getOperand(Elt.getResNo()).Val;
>> + return Elt.getNode();
>> + return Elt.getOperand(Elt.getResNo()).getNode();
>> }
>>
>> /// CombineConsecutiveLoads - build_pair (load, load) -> load
>> @@ -3434,7 +3434,7 @@
>> // on the bitconvert.
>> // First check to see if this is all constant.
>> if (!AfterLegalize &&
>> - N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() &&
>> + N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()-
>>> hasOneUse() &&
>> VT.isVector()) {
>> bool isSimple = true;
>> for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
>> @@ -3449,14 +3449,14 @@
>> assert(!DestEltVT.isVector() &&
>> "Element type of vector ValueType must not be vector!");
>> if (isSimple) {
>> - return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val,
>> DestEltVT);
>> + return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(),
>> DestEltVT);
>> }
>> }
>>
>> // If the input is a constant, let getNode() fold it.
>> if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
>> SDValue Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
>> - if (Res.Val != N) return Res;
>> + if (Res.getNode() != N) return Res;
>> }
>>
>> if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) ->
>> conv(x,t2)
>> @@ -3464,7 +3464,7 @@
>>
>> // fold (conv (load x)) -> (load (conv*)x)
>> // If the resultant load doesn't need a higher alignment than the
>> original!
>> - if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() &&
>> + if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
>> // Do not change the width of a volatile load.
>> !cast<LoadSDNode>(N0)->isVolatile() &&
>> (!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT))) {
>> @@ -3477,7 +3477,7 @@
>> LN0->getSrcValue(), LN0-
>>> getSrcValueOffset(),
>> LN0->isVolatile(), OrigAlign);
>> AddToWorkList(N);
>> - CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT,
>> N0.getValueType(), Load),
>> + CombineTo(N0.getNode(), DAG.getNode(ISD::BIT_CONVERT,
>> N0.getValueType(), Load),
>> Load.getValue(1));
>> return Load;
>> }
>> @@ -3487,9 +3487,9 @@
>> // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit)
>> // This often reduces constant pool loads.
>> if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
>> - N0.Val->hasOneUse() && VT.isInteger() && !VT.isVector()) {
>> + N0.getNode()->hasOneUse() && VT.isInteger() && !
>> VT.isVector()) {
>> SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, VT,
>> N0.getOperand(0));
>> - AddToWorkList(NewConv.Val);
>> + AddToWorkList(NewConv.getNode());
>>
>> APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
>> if (N0.getOpcode() == ISD::FNEG)
>> @@ -3501,45 +3501,45 @@
>> // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign |
>> cst&~sign'
>> // Note that we don't handle copysign(x,cst) because this can
>> always be folded
>> // to an fneg or fabs.
>> - if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse() &&
>> + if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()
>> &&
>> isa<ConstantFPSDNode>(N0.getOperand(0)) &&
>> VT.isInteger() && !VT.isVector()) {
>> unsigned OrigXWidth =
>> N0.getOperand(1).getValueType().getSizeInBits();
>> SDValue X = DAG.getNode(ISD::BIT_CONVERT,
>> MVT::getIntegerVT(OrigXWidth),
>> N0.getOperand(1));
>> - AddToWorkList(X.Val);
>> + AddToWorkList(X.getNode());
>>
>> // If X has a different width than the result/lhs, sext it or
>> truncate it.
>> unsigned VTWidth = VT.getSizeInBits();
>> if (OrigXWidth < VTWidth) {
>> X = DAG.getNode(ISD::SIGN_EXTEND, VT, X);
>> - AddToWorkList(X.Val);
>> + AddToWorkList(X.getNode());
>> } else if (OrigXWidth > VTWidth) {
>> // To get the sign bit in the right place, we have to shift it
>> right
>> // before truncating.
>> X = DAG.getNode(ISD::SRL, X.getValueType(), X,
>> DAG.getConstant(OrigXWidth-VTWidth,
>> X.getValueType()));
>> - AddToWorkList(X.Val);
>> + AddToWorkList(X.getNode());
>> X = DAG.getNode(ISD::TRUNCATE, VT, X);
>> - AddToWorkList(X.Val);
>> + AddToWorkList(X.getNode());
>> }
>>
>> APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
>> X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT));
>> - AddToWorkList(X.Val);
>> + AddToWorkList(X.getNode());
>>
>> SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
>> Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit,
>> VT));
>> - AddToWorkList(Cst.Val);
>> + AddToWorkList(Cst.getNode());
>>
>> return DAG.getNode(ISD::OR, VT, X, Cst);
>> }
>>
>> // bitconvert(build_pair(ld, ld)) -> ld iff load locations are
>> consecutive.
>> if (N0.getOpcode() == ISD::BUILD_PAIR) {
>> - SDValue CombineLD = CombineConsecutiveLoads(N0.Val, VT);
>> - if (CombineLD.Val)
>> + SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
>> + if (CombineLD.getNode())
>> return CombineLD;
>> }
>>
>> @@ -3570,7 +3570,7 @@
>> SmallVector<SDValue, 8> Ops;
>> for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
>> Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV-
>>> getOperand(i)));
>> - AddToWorkList(Ops.back().Val);
>> + AddToWorkList(Ops.back().getNode());
>> }
>> MVT VT = MVT::getVectorVT(DstEltVT,
>> BV-
>>> getValueType(0).getVectorNumElements());
>> @@ -3585,7 +3585,7 @@
>> // same sizes.
>> assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) &&
>> "Unknown FP VT!");
>> MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits());
>> - BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val;
>> + BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
>> SrcEltVT = IntVT;
>> }
>>
>> @@ -3594,7 +3594,7 @@
>> if (DstEltVT.isFloatingPoint()) {
>> assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) &&
>> "Unknown FP VT!");
>> MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits());
>> - SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV,
>> TmpVT).Val;
>> + SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV,
>> TmpVT).getNode();
>>
>> // Next, convert to FP elements of the same size.
>> return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
>> @@ -3674,7 +3674,7 @@
>> // fold vector ops
>> if (VT.isVector()) {
>> SDValue FoldedVOp = SimplifyVBinOp(N);
>> - if (FoldedVOp.Val) return FoldedVOp;
>> + if (FoldedVOp.getNode()) return FoldedVOp;
>> }
>>
>> // fold (fadd c1, c2) -> c1+c2
>> @@ -3694,7 +3694,7 @@
>>
>> // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1,
>> c2))
>> if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
>> - N0.Val->hasOneUse() &&
>> isa<ConstantFPSDNode>(N0.getOperand(1)))
>> + N0.getNode()->hasOneUse() &&
>> isa<ConstantFPSDNode>(N0.getOperand(1)))
>> return DAG.getNode(ISD::FADD, VT, N0.getOperand(0),
>> DAG.getNode(ISD::FADD, VT, N0.getOperand(1),
>> N1));
>>
>> @@ -3711,7 +3711,7 @@
>> // fold vector ops
>> if (VT.isVector()) {
>> SDValue FoldedVOp = SimplifyVBinOp(N);
>> - if (FoldedVOp.Val) return FoldedVOp;
>> + if (FoldedVOp.getNode()) return FoldedVOp;
>> }
>>
>> // fold (fsub c1, c2) -> c1-c2
>> @@ -3741,7 +3741,7 @@
>> // fold vector ops
>> if (VT.isVector()) {
>> SDValue FoldedVOp = SimplifyVBinOp(N);
>> - if (FoldedVOp.Val) return FoldedVOp;
>> + if (FoldedVOp.getNode()) return FoldedVOp;
>> }
>>
>> // fold (fmul c1, c2) -> c1*c2
>> @@ -3771,7 +3771,7 @@
>>
>> // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1,
>> c2))
>> if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
>> - N0.Val->hasOneUse() &&
>> isa<ConstantFPSDNode>(N0.getOperand(1)))
>> + N0.getNode()->hasOneUse() &&
>> isa<ConstantFPSDNode>(N0.getOperand(1)))
>> return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0),
>> DAG.getNode(ISD::FMUL, VT, N0.getOperand(1),
>> N1));
>>
>> @@ -3788,7 +3788,7 @@
>> // fold vector ops
>> if (VT.isVector()) {
>> SDValue FoldedVOp = SimplifyVBinOp(N);
>> - if (FoldedVOp.Val) return FoldedVOp;
>> + if (FoldedVOp.getNode()) return FoldedVOp;
>> }
>>
>> // fold (fdiv c1, c2) -> c1/c2
>> @@ -3955,15 +3955,15 @@
>> if (N0.getOpcode() == ISD::FP_ROUND) {
>> // This is a value preserving truncation if both round's are.
>> bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
>> - N0.Val->getConstantOperandVal(1) == 1;
>> + N0.getNode()->getConstantOperandVal(1) == 1;
>> return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0),
>> DAG.getIntPtrConstant(IsTrunc));
>> }
>>
>> // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
>> - if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
>> + if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()-
>>> hasOneUse()) {
>> SDValue Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0),
>> N1);
>> - AddToWorkList(Tmp.Val);
>> + AddToWorkList(Tmp.getNode());
>> return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
>> }
>>
>> @@ -4000,7 +4000,7 @@
>>
>> // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't
>> affect the
>> // value of X.
>> - if (N0.getOpcode() == ISD::FP_ROUND && N0.Val-
>>> getConstantOperandVal(1) == 1){
>> + if (N0.getOpcode() == ISD::FP_ROUND && N0.getNode()-
>>> getConstantOperandVal(1) == 1){
>> SDValue In = N0.getOperand(0);
>> if (In.getValueType() == VT) return In;
>> if (VT.bitsLT(In.getValueType()))
>> @@ -4009,7 +4009,7 @@
>> }
>>
>> // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
>> - if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
>> + if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
>> ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
>> TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
>> LoadSDNode *LN0 = cast<LoadSDNode>(N0);
>> @@ -4020,7 +4020,7 @@
>> LN0->isVolatile(),
>> LN0->getAlignment());
>> CombineTo(N, ExtLoad);
>> - CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(),
>> ExtLoad,
>> + CombineTo(N0.getNode(), DAG.getNode(ISD::FP_ROUND,
>> N0.getValueType(), ExtLoad,
>> DAG.getIntPtrConstant(1)),
>> ExtLoad.getValue(1));
>> return SDValue(N, 0); // Return N so it doesn't get rechecked!
>> @@ -4037,7 +4037,7 @@
>>
>> // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid
>> loading
>> // constant pool values.
>> - if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() &&
>> + if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()-
>>> hasOneUse() &&
>> N0.getOperand(0).getValueType().isInteger() &&
>> !N0.getOperand(0).getValueType().isVector()) {
>> SDValue Int = N0.getOperand(0);
>> @@ -4045,7 +4045,7 @@
>> if (IntVT.isInteger() && !IntVT.isVector()) {
>> Int = DAG.getNode(ISD::XOR, IntVT, Int,
>> DAG.getConstant(IntVT.getIntegerVTSignBit(),
>> IntVT));
>> - AddToWorkList(Int.Val);
>> + AddToWorkList(Int.getNode());
>> return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int);
>> }
>> }
>> @@ -4071,7 +4071,7 @@
>>
>> // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid
>> loading
>> // constant pool values.
>> - if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() &&
>> + if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()-
>>> hasOneUse() &&
>> N0.getOperand(0).getValueType().isInteger() &&
>> !N0.getOperand(0).getValueType().isVector()) {
>> SDValue Int = N0.getOperand(0);
>> @@ -4079,7 +4079,7 @@
>> if (IntVT.isInteger() && !IntVT.isVector()) {
>> Int = DAG.getNode(ISD::AND, IntVT, Int,
>>
>> DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT));
>> - AddToWorkList(Int.Val);
>> + AddToWorkList(Int.getNode());
>> return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int);
>> }
>> }
>> @@ -4117,9 +4117,9 @@
>>
>> // Use SimplifySetCC to simplify SETCC's.
>> SDValue Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(),
>> false);
>> - if (Simp.Val) AddToWorkList(Simp.Val);
>> + if (Simp.getNode()) AddToWorkList(Simp.getNode());
>>
>> - ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
>> + ConstantSDNode *SCCC =
>> dyn_cast_or_null<ConstantSDNode>(Simp.getNode());
>>
>> // fold br_cc true, dest -> br dest (unconditional branch)
>> if (SCCC && !SCCC->isNullValue())
>> @@ -4130,7 +4130,7 @@
>> return N->getOperand(0);
>>
>> // fold to a simpler setcc
>> - if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
>> + if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
>> return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
>> Simp.getOperand(2), Simp.getOperand(0),
>> Simp.getOperand(1), N->getOperand(4));
>> @@ -4174,7 +4174,7 @@
>> // If the pointer is not an add/sub, or if it doesn't have
>> multiple uses, bail
>> // out. There is no reason to make this a preinc/predec.
>> if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
>> - Ptr.Val->hasOneUse())
>> + Ptr.getNode()->hasOneUse())
>> return false;
>>
>> // Ask the target to do addressing mode selection.
>> @@ -4204,14 +4204,14 @@
>> // Check #2.
>> if (!isLoad) {
>> SDValue Val = cast<StoreSDNode>(N)->getValue();
>> - if (Val == BasePtr || BasePtr.Val->isPredecessorOf(Val.Val))
>> + if (Val == BasePtr || BasePtr.getNode()-
>>> isPredecessorOf(Val.getNode()))
>> return false;
>> }
>>
>> // Now check for #3 and #4.
>> bool RealUse = false;
>> - for (SDNode::use_iterator I = Ptr.Val->use_begin(),
>> - E = Ptr.Val->use_end(); I != E; ++I) {
>> + for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
>> + E = Ptr.getNode()->use_end(); I != E; ++I) {
>> SDNode *Use = *I;
>> if (Use == N)
>> continue;
>> @@ -4235,7 +4235,7 @@
>> ++PreIndexedNodes;
>> ++NodesCombined;
>> DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
>> - DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
>> + DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG));
>> DOUT << '\n';
>> WorkListRemover DeadNodes(*this);
>> if (isLoad) {
>> @@ -4254,8 +4254,8 @@
>> // Replace the uses of Ptr with uses of the updated base value.
>> DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
>> &DeadNodes);
>> - removeFromWorkList(Ptr.Val);
>> - DAG.DeleteNode(Ptr.Val);
>> + removeFromWorkList(Ptr.getNode());
>> + DAG.DeleteNode(Ptr.getNode());
>>
>> return true;
>> }
>> @@ -4292,11 +4292,11 @@
>> } else
>> return false;
>>
>> - if (Ptr.Val->hasOneUse())
>> + if (Ptr.getNode()->hasOneUse())
>> return false;
>>
>> - for (SDNode::use_iterator I = Ptr.Val->use_begin(),
>> - E = Ptr.Val->use_end(); I != E; ++I) {
>> + for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
>> + E = Ptr.getNode()->use_end(); I != E; ++I) {
>> SDNode *Op = *I;
>> if (Op == N ||
>> (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
>> @@ -4323,10 +4323,10 @@
>>
>> // Check for #1.
>> bool TryNext = false;
>> - for (SDNode::use_iterator II = BasePtr.Val->use_begin(),
>> - EE = BasePtr.Val->use_end(); II != EE; ++II) {
>> + for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
>> + EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
>> SDNode *Use = *II;
>> - if (Use == Ptr.Val)
>> + if (Use == Ptr.getNode())
>> continue;
>>
>> // If all the uses are load / store addresses, then don't do
>> the
>> @@ -4337,9 +4337,9 @@
>> EEE = Use->use_end(); III != EEE; ++III) {
>> SDNode *UseUse = *III;
>> if (!((UseUse->getOpcode() == ISD::LOAD &&
>> - cast<LoadSDNode>(UseUse)->getBasePtr().Val ==
>> Use) ||
>> + cast<LoadSDNode>(UseUse)->getBasePtr().getNode()
>> == Use) ||
>> (UseUse->getOpcode() == ISD::STORE &&
>> - cast<StoreSDNode>(UseUse)->getBasePtr().Val ==
>> Use)))
>> + cast<StoreSDNode>(UseUse)-
>>> getBasePtr().getNode() == Use)))
>> RealUse = true;
>> }
>>
>> @@ -4360,7 +4360,7 @@
>> ++PostIndexedNodes;
>> ++NodesCombined;
>> DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
>> - DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
>> + DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG));
>> DOUT << '\n';
>> WorkListRemover DeadNodes(*this);
>> if (isLoad) {
>> @@ -4463,7 +4463,7 @@
>> // Now we replace use of chain2 with chain1. This makes the
>> second load
>> // isomorphic to the one we are deleting, and thus makes
>> this load live.
>> DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
>> - DOUT << "\nWith chain: "; DEBUG(Chain.Val->dump(&DAG));
>> + DOUT << "\nWith chain: "; DEBUG(Chain.getNode()-
>> >dump(&DAG));
>> DOUT << "\n";
>> WorkListRemover DeadNodes(*this);
>> DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain,
>> &DeadNodes);
>> @@ -4479,7 +4479,7 @@
>> if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
>> SDValue Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0));
>> DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
>> - DOUT << "\nWith: "; DEBUG(Undef.Val->dump(&DAG));
>> + DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG));
>> DOUT << " and 2 other values\n";
>> WorkListRemover DeadNodes(*this);
>> DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef,
>> &DeadNodes);
>> @@ -4500,7 +4500,7 @@
>> // TODO: Handle TRUNCSTORE/LOADEXT
>> if (LD->getExtensionType() == ISD::NON_EXTLOAD &&
>> !LD->isVolatile()) {
>> - if (ISD::isNON_TRUNCStore(Chain.Val)) {
>> + if (ISD::isNON_TRUNCStore(Chain.getNode())) {
>> StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
>> if (PrevST->getBasePtr() == Ptr &&
>> PrevST->getValue().getValueType() == N->getValueType(0))
>> @@ -4684,8 +4684,8 @@
>> GetDemandedBits(Value,
>> APInt::getLowBitsSet(Value.getValueSizeInBits(),
>> ST-
>>> getMemoryVT().getSizeInBits()));
>> - AddToWorkList(Value.Val);
>> - if (Shorter.Val)
>> + AddToWorkList(Value.getNode());
>> + if (Shorter.getNode())
>> return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(),
>> ST->getSrcValueOffset(), ST-
>>> getMemoryVT(),
>> ST->isVolatile(), ST->getAlignment());
>> @@ -4715,7 +4715,7 @@
>> // If this is an FP_ROUND or TRUNC followed by a store, fold this
>> into a
>> // truncating store. We can do this even if this is already a
>> truncstore.
>> if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() ==
>> ISD::TRUNCATE)
>> - && Value.Val->hasOneUse() && ST->isUnindexed() &&
>> + && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
>> TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
>> ST->getMemoryVT())) {
>> return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST-
>>> getSrcValue(),
>> @@ -4735,7 +4735,7 @@
>> // vector with the inserted element.
>> if (InVec.getOpcode() == ISD::BUILD_VECTOR &&
>> isa<ConstantSDNode>(EltNo)) {
>> unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
>> - SmallVector<SDValue, 8> Ops(InVec.Val->op_begin(), InVec.Val-
>>> op_end());
>> + SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
>> InVec.getNode()->op_end());
>> if (Elt < Ops.size())
>> Ops[Elt] = InVal;
>> return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
>> @@ -4773,11 +4773,11 @@
>> }
>>
>> LoadSDNode *LN0 = NULL;
>> - if (ISD::isNormalLoad(InVec.Val))
>> + if (ISD::isNormalLoad(InVec.getNode()))
>> LN0 = cast<LoadSDNode>(InVec);
>> else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
>> InVec.getOperand(0).getValueType() == EVT &&
>> - ISD::isNormalLoad(InVec.getOperand(0).Val)) {
>> + ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
>> LN0 = cast<LoadSDNode>(InVec.getOperand(0));
>> } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) {
>> // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
>> @@ -4789,7 +4789,7 @@
>> InVec = (Idx < NumElems) ? InVec.getOperand(0) :
>> InVec.getOperand(1);
>> if (InVec.getOpcode() == ISD::BIT_CONVERT)
>> InVec = InVec.getOperand(0);
>> - if (ISD::isNormalLoad(InVec.Val)) {
>> + if (ISD::isNormalLoad(InVec.getNode())) {
>> LN0 = cast<LoadSDNode>(InVec);
>> Elt = (Idx < NumElems) ? Idx : Idx - NumElems;
>> }
>> @@ -4859,9 +4859,9 @@
>> if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
>> continue;
>>
>> - if (VecIn1.Val == 0) {
>> + if (VecIn1.getNode() == 0) {
>> VecIn1 = ExtractedFromVec;
>> - } else if (VecIn2.Val == 0) {
>> + } else if (VecIn2.getNode() == 0) {
>> VecIn2 = ExtractedFromVec;
>> } else {
>> // Too many inputs.
>> @@ -4871,7 +4871,7 @@
>> }
>>
>> // If everything is good, we can make a shuffle operation.
>> - if (VecIn1.Val) {
>> + if (VecIn1.getNode()) {
>> SmallVector<SDValue, 8> BuildVecIndices;
>> for (unsigned i = 0; i != NumInScalars; ++i) {
>> if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
>> @@ -4898,7 +4898,7 @@
>> // Return the new VECTOR_SHUFFLE node.
>> SDValue Ops[5];
>> Ops[0] = VecIn1;
>> - if (VecIn2.Val) {
>> + if (VecIn2.getNode()) {
>> Ops[1] = VecIn2;
>> } else {
>> // Use an undef build_vector as input for the second operand.
>> @@ -4907,7 +4907,7 @@
>> EltType));
>> Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT,
>> &UnOps[0], UnOps.size());
>> - AddToWorkList(Ops[1].Val);
>> + AddToWorkList(Ops[1].getNode());
>> }
>> Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT,
>> &BuildVecIndices[0], BuildVecIndices.size());
>> @@ -4989,7 +4989,7 @@
>> // If it is a splat, check if the argument vector is a
>> build_vector with
>> // all scalar elements the same.
>> if (isSplat) {
>> - SDNode *V = N0.Val;
>> + SDNode *V = N0.getNode();
>>
>> // If this is a bit convert that changes the element type of the
>> vector but
>> // not the number of vector elements, look through it. Be
>> careful not to
>> @@ -4998,7 +4998,7 @@
>> SDValue ConvInput = V->getOperand(0);
>> if (ConvInput.getValueType().isVector() &&
>> ConvInput.getValueType().getVectorNumElements() == NumElts)
>> - V = ConvInput.Val;
>> + V = ConvInput.getNode();
>> }
>>
>> if (V->getOpcode() == ISD::BUILD_VECTOR) {
>> @@ -5013,7 +5013,7 @@
>> }
>> }
>> // Splat of <u, u, u, u>, return <u, u, u, u>
>> - if (!Base.Val)
>> + if (!Base.getNode())
>> return N0;
>> for (unsigned i = 0; i != NumElems; ++i) {
>> if (V->getOperand(i) != Base) {
>> @@ -5047,7 +5047,7 @@
>> }
>> ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
>> &MappedOps[0], MappedOps.size());
>> - AddToWorkList(ShufMask.Val);
>> + AddToWorkList(ShufMask.getNode());
>> return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
>> N0,
>> DAG.getNode(ISD::UNDEF, N->getValueType(0)),
>> @@ -5093,7 +5093,7 @@
>> std::vector<SDValue> Ops;
>> LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS);
>> Ops.push_back(LHS);
>> - AddToWorkList(LHS.Val);
>> + AddToWorkList(LHS.getNode());
>> std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT));
>> Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
>> &ZeroOps[0], ZeroOps.size()));
>> @@ -5123,7 +5123,7 @@
>> SDValue LHS = N->getOperand(0);
>> SDValue RHS = N->getOperand(1);
>> SDValue Shuffle = XformToShuffleWithZero(N);
>> - if (Shuffle.Val) return Shuffle;
>> + if (Shuffle.getNode()) return Shuffle;
>>
>> // If the LHS and RHS are BUILD_VECTOR nodes, see if we can
>> constant fold
>> // this operation.
>> @@ -5145,13 +5145,13 @@
>> if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV
>> ||
>> N->getOpcode() == ISD::FDIV) {
>> if ((RHSOp.getOpcode() == ISD::Constant &&
>> - cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
>> + cast<ConstantSDNode>(RHSOp.getNode())->isNullValue())
>> ||
>> (RHSOp.getOpcode() == ISD::ConstantFP &&
>> - cast<ConstantFPSDNode>(RHSOp.Val)-
>>> getValueAPF().isZero()))
>> + cast<ConstantFPSDNode>(RHSOp.getNode())-
>>> getValueAPF().isZero()))
>> break;
>> }
>> Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp,
>> RHSOp));
>> - AddToWorkList(Ops.back().Val);
>> + AddToWorkList(Ops.back().getNode());
>> assert((Ops.back().getOpcode() == ISD::UNDEF ||
>> Ops.back().getOpcode() == ISD::Constant ||
>> Ops.back().getOpcode() == ISD::ConstantFP) &&
>> @@ -5175,14 +5175,14 @@
>> // If we got a simplified select_cc node back from
>> SimplifySelectCC, then
>> // break it down into a new SETCC node, and a new SELECT node, and
>> then return
>> // the SELECT node, since we were called with a SELECT node.
>> - if (SCC.Val) {
>> + if (SCC.getNode()) {
>> // Check to see if we got a select_cc back (to turn into setcc/
>> select).
>> // Otherwise, just return whatever node we got back, like fabs.
>> if (SCC.getOpcode() == ISD::SELECT_CC) {
>> SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
>> SCC.getOperand(0),
>> SCC.getOperand(1),
>> SCC.getOperand(4));
>> - AddToWorkList(SETCC.Val);
>> + AddToWorkList(SETCC.getNode());
>> return DAG.getNode(ISD::SELECT, SCC.getValueType(),
>> SCC.getOperand(2),
>> SCC.getOperand(3), SETCC);
>> }
>> @@ -5226,8 +5226,8 @@
>> if (TheSelect->getOpcode() == ISD::SELECT) {
>> // Check that the condition doesn't reach either load. If
>> so, folding
>> // this will induce a cycle into the DAG.
>> - if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) &&
>> - !RLD->isPredecessorOf(TheSelect->getOperand(0).Val)) {
>> + if (!LLD->isPredecessorOf(TheSelect-
>>> getOperand(0).getNode()) &&
>> + !RLD->isPredecessorOf(TheSelect-
>>> getOperand(0).getNode())) {
>> Addr = DAG.getNode(ISD::SELECT, LLD-
>>> getBasePtr().getValueType(),
>> TheSelect->getOperand(0), LLD-
>>> getBasePtr(),
>> RLD->getBasePtr());
>> @@ -5235,10 +5235,10 @@
>> } else {
>> // Check that the condition doesn't reach either load. If
>> so, folding
>> // this will induce a cycle into the DAG.
>> - if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) &&
>> - !RLD->isPredecessorOf(TheSelect->getOperand(0).Val) &&
>> - !LLD->isPredecessorOf(TheSelect->getOperand(1).Val) &&
>> - !RLD->isPredecessorOf(TheSelect->getOperand(1).Val)) {
>> + if (!LLD->isPredecessorOf(TheSelect-
>>> getOperand(0).getNode()) &&
>> + !RLD->isPredecessorOf(TheSelect-
>>> getOperand(0).getNode()) &&
>> + !LLD->isPredecessorOf(TheSelect-
>>> getOperand(1).getNode()) &&
>> + !RLD->isPredecessorOf(TheSelect-
>>> getOperand(1).getNode())) {
>> Addr = DAG.getNode(ISD::SELECT_CC, LLD-
>>> getBasePtr().getValueType(),
>> TheSelect->getOperand(0),
>> TheSelect->getOperand(1),
>> @@ -5247,7 +5247,7 @@
>> }
>> }
>>
>> - if (Addr.Val) {
>> + if (Addr.getNode()) {
>> SDValue Load;
>> if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
>> Load = DAG.getLoad(TheSelect->getValueType(0), LLD-
>>> getChain(),
>> @@ -5269,8 +5269,8 @@
>>
>> // Users of the old loads now use the new load's chain.
>> We know the
>> // old-load value is dead now.
>> - CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
>> - CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
>> + CombineTo(LHS.getNode(), Load.getValue(0),
>> Load.getValue(1));
>> + CombineTo(RHS.getNode(), Load.getValue(0),
>> Load.getValue(1));
>> return true;
>> }
>> }
>> @@ -5285,14 +5285,14 @@
>> ISD::CondCode CC, bool
>> NotExtCompare) {
>>
>> MVT VT = N2.getValueType();
>> - ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
>> - ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
>> - ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
>> + ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
>> + ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
>> + ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
>>
>> // Determine if the condition we're dealing with is constant
>> SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1,
>> CC, false);
>> - if (SCC.Val) AddToWorkList(SCC.Val);
>> - ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
>> + if (SCC.getNode()) AddToWorkList(SCC.getNode());
>> + ConstantSDNode *SCCC =
>> dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
>>
>> // fold select_cc true, x, y -> x
>> if (SCCC && !SCCC->isNullValue())
>> @@ -5336,20 +5336,20 @@
>> ShCtV = XType.getSizeInBits()-ShCtV-1;
>> SDValue ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
>> SDValue Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
>> - AddToWorkList(Shift.Val);
>> + AddToWorkList(Shift.getNode());
>> if (XType.bitsGT(AType)) {
>> Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
>> - AddToWorkList(Shift.Val);
>> + AddToWorkList(Shift.getNode());
>> }
>> return DAG.getNode(ISD::AND, AType, Shift, N2);
>> }
>> SDValue Shift = DAG.getNode(ISD::SRA, XType, N0,
>>
>> DAG.getConstant(XType.getSizeInBits()-1,
>>
>> TLI.getShiftAmountTy()));
>> - AddToWorkList(Shift.Val);
>> + AddToWorkList(Shift.getNode());
>> if (XType.bitsGT(AType)) {
>> Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
>> - AddToWorkList(Shift.Val);
>> + AddToWorkList(Shift.getNode());
>> }
>> return DAG.getNode(ISD::AND, AType, Shift, N2);
>> }
>> @@ -5379,8 +5379,8 @@
>> SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
>> Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
>> }
>> - AddToWorkList(SCC.Val);
>> - AddToWorkList(Temp.Val);
>> + AddToWorkList(SCC.getNode());
>> + AddToWorkList(Temp.getNode());
>>
>> if (N2C->getAPIntValue() == 1)
>> return Temp;
>> @@ -5442,8 +5442,8 @@
>>
>> DAG.getConstant(XType.getSizeInBits()-1,
>>
>> TLI.getShiftAmountTy()));
>> SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
>> - AddToWorkList(Shift.Val);
>> - AddToWorkList(Add.Val);
>> + AddToWorkList(Shift.getNode());
>> + AddToWorkList(Add.getNode());
>> return DAG.getNode(ISD::XOR, XType, Add, Shift);
>> }
>> // Check to see if this is an integer abs. select_cc setgt X, -1,
>> X, -X ->
>> @@ -5457,8 +5457,8 @@
>>
>> DAG.getConstant(XType.getSizeInBits()-1,
>>
>> TLI.getShiftAmountTy()));
>> SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
>> - AddToWorkList(Shift.Val);
>> - AddToWorkList(Add.Val);
>> + AddToWorkList(Shift.getNode());
>> + AddToWorkList(Add.getNode());
>> return DAG.getNode(ISD::XOR, XType, Add, Shift);
>> }
>> }
>> @@ -5612,8 +5612,8 @@
>> Chains.pop_back();
>>
>> // Don't bother if we've been before.
>> - if (Visited.find(Chain.Val) != Visited.end()) continue;
>> - Visited.insert(Chain.Val);
>> + if (Visited.find(Chain.getNode()) != Visited.end()) continue;
>> + Visited.insert(Chain.getNode());
>>
>> switch (Chain.getOpcode()) {
>> case ISD::EntryToken:
>> @@ -5627,7 +5627,7 @@
>> int64_t OpSize;
>> const Value *OpSrcValue;
>> int OpSrcValueOffset;
>> - bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize,
>> + bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
>> OpSrcValue, OpSrcValueOffset);
>>
>> // If chain is alias then stop here.
>> @@ -5639,7 +5639,7 @@
>> // Look further up the chain.
>> Chains.push_back(Chain.getOperand(0));
>> // Clean up old chain.
>> - AddToWorkList(Chain.Val);
>> + AddToWorkList(Chain.getNode());
>> }
>> break;
>> }
>> @@ -5652,7 +5652,7 @@
>> for (unsigned n = Chain.getNumOperands(); n;)
>> Chains.push_back(Chain.getOperand(--n));
>> // Eliminate the token factor if we can.
>> - AddToWorkList(Chain.Val);
>> + AddToWorkList(Chain.getNode());
>> break;
>>
>> default:
>> @@ -5684,7 +5684,7 @@
>> &Aliases[0], Aliases.size());
>>
>> // Make sure the old chain gets cleaned up.
>> - if (NewChain != OldChain) AddToWorkList(OldChain.Val);
>> + if (NewChain != OldChain) AddToWorkList(OldChain.getNode());
>>
>> return NewChain;
>> }
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -260,7 +260,7 @@
>> break;
>> }
>> }
>> - return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
>> + return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
>> }
>>
>> SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
>> @@ -350,7 +350,7 @@
>>
>> assert(Node->getOperand(0).getValueType() == MVT::Other &&
>> "Node doesn't have a token chain argument!");
>> - return FindCallStartFromCallEnd(Node->getOperand(0).Val);
>> + return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
>> }
>>
>> /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N,
>> looking to
>> @@ -387,7 +387,7 @@
>> bool OperandsLeadToDest = false;
>> for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
>> OperandsLeadToDest |= // If an operand leads to Dest, so do
>> we.
>> - LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest,
>> NodesLeadingTo);
>> + LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(),
>> Dest, NodesLeadingTo);
>>
>> if (OperandsLeadToDest) {
>> NodesLeadingTo.insert(N);
>> @@ -667,7 +667,7 @@
>> MVT VT = Op.getValueType();
>> assert(isTypeLegal(VT) &&
>> "Caller should expand or promote operands that are not
>> legal!");
>> - assert(Op.Val->getNumValues() == 1 &&
>> + assert(Op.getNode()->getNumValues() == 1 &&
>> "Can't unroll a vector with multiple results!");
>> unsigned NE = VT.getVectorNumElements();
>> MVT EltVT = VT.getVectorElementType();
>> @@ -733,7 +733,7 @@
>> MVT PtrVT = TLI.getPointerTy();
>> SDValue StackPtr = DAG.CreateStackTemporary(VT);
>>
>> - int SPFI = cast<FrameIndexSDNode>(StackPtr.Val)->getIndex();
>> + int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
>>
>> // Store the vector.
>> SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
>> @@ -764,7 +764,7 @@
>>
>> assert(isTypeLegal(Op.getValueType()) &&
>> "Caller should expand or promote operands that are not
>> legal!");
>> - SDNode *Node = Op.Val;
>> + SDNode *Node = Op.getNode();
>>
>> // If this operation defines any values that cannot be represented
>> in a
>> // register on this target, make sure to expand or promote them.
>> @@ -839,7 +839,7 @@
>> default: assert(0 && "This action is not supported yet!");
>> case TargetLowering::Custom:
>> Tmp1 = TLI.LowerOperation(Op, DAG);
>> - if (Tmp1.Val) Result = Tmp1;
>> + if (Tmp1.getNode()) Result = Tmp1;
>> // FALLTHROUGH if the target doesn't want to lower this op
>> after all.
>> case TargetLowering::Legal:
>> break;
>> @@ -850,7 +850,7 @@
>> // The only option for these nodes is to custom lower them. If
>> the target
>> // does not custom lower them, then return zero.
>> Tmp1 = TLI.LowerOperation(Op, DAG);
>> - if (Tmp1.Val)
>> + if (Tmp1.getNode())
>> Result = Tmp1;
>> else
>> Result = DAG.getConstant(0, TLI.getPointerTy());
>> @@ -861,7 +861,7 @@
>> default: assert(0 && "This action is not supported yet!");
>> case TargetLowering::Custom:
>> Result = TLI.LowerOperation(Op, DAG);
>> - if (Result.Val) break;
>> + if (Result.getNode()) break;
>> // Fall Thru
>> case TargetLowering::Legal:
>> Result = DAG.getConstant(0, VT);
>> @@ -881,7 +881,7 @@
>> break;
>> case TargetLowering::Custom:
>> Result = TLI.LowerOperation(Op, DAG);
>> - if (Result.Val) break;
>> + if (Result.getNode()) break;
>> // Fall Thru
>> case TargetLowering::Legal: {
>> SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
>> @@ -890,9 +890,9 @@
>> }
>> }
>> }
>> - if (Result.Val->getNumValues() == 1) break;
>> + if (Result.getNode()->getNumValues() == 1) break;
>>
>> - assert(Result.Val->getNumValues() == 2 &&
>> + assert(Result.getNode()->getNumValues() == 2 &&
>> "Cannot return more than two values!");
>>
>> // Since we produced two values, make sure to remember that we
>> @@ -915,7 +915,7 @@
>> break;
>> case TargetLowering::Custom:
>> Result = TLI.LowerOperation(Op, DAG);
>> - if (Result.Val) break;
>> + if (Result.getNode()) break;
>> // Fall Thru
>> case TargetLowering::Legal: {
>> SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
>> @@ -924,9 +924,9 @@
>> }
>> }
>> }
>> - if (Result.Val->getNumValues() == 1) break;
>> + if (Result.getNode()->getNumValues() == 1) break;
>>
>> - assert(Result.Val->getNumValues() == 2 &&
>> + assert(Result.getNode()->getNumValues() == 2 &&
>> "Cannot return more than two values!");
>>
>> // Since we produced two values, make sure to remember that we
>> @@ -943,7 +943,7 @@
>> default: assert(0 && "This action is not supported at all!");
>> case TargetLowering::Custom:
>> Result = TLI.LowerOperation(Op, DAG);
>> - if (Result.Val) break;
>> + if (Result.getNode()) break;
>> // Fall Thru
>> case TargetLowering::Legal:
>> // Target does not know, how to lower this, lower to noop
>> @@ -1012,13 +1012,13 @@
>> if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
>> TargetLowering::Custom) {
>> Tmp3 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp3.Val) Result = Tmp3;
>> + if (Tmp3.getNode()) Result = Tmp3;
>> }
>>
>> - if (Result.Val->getNumValues() == 1) break;
>> + if (Result.getNode()->getNumValues() == 1) break;
>>
>> // Must have return value and chain result.
>> - assert(Result.Val->getNumValues() == 2 &&
>> + assert(Result.getNode()->getNumValues() == 2 &&
>> "Cannot return more than two values!");
>>
>> // Since loads produce two values, make sure to remember that we
>> @@ -1261,7 +1261,7 @@
>> Result = TLI.LowerOperation(Result, DAG);
>> break;
>> case TargetLowering::Expand:
>> - Result = SDValue(TLI.ReplaceNodeResults(Op.Val, DAG),0);
>> + Result = SDValue(TLI.ReplaceNodeResults(Op.getNode(), DAG),0);
>> break;
>> case TargetLowering::Legal:
>> break;
>> @@ -1280,7 +1280,7 @@
>>
>> if (opAction == TargetLowering::Custom) {
>> Tmp1 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp1.Val)
>> + if (Tmp1.getNode())
>> Result = Tmp1;
>> }
>> break;
>> @@ -1298,7 +1298,7 @@
>> break;
>> case TargetLowering::Custom:
>> Tmp3 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp3.Val) {
>> + if (Tmp3.getNode()) {
>> Result = Tmp3;
>> break;
>> }
>> @@ -1344,27 +1344,27 @@
>> case ISD::CALL:
>> // The only option for this is to custom lower it.
>> Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
>> - assert(Tmp3.Val && "Target didn't custom lower this node!");
>> + assert(Tmp3.getNode() && "Target didn't custom lower this
>> node!");
>> // A call within a calling sequence must be legalized to something
>> // other than the normal CALLSEQ_END. Violating this gets
>> Legalize
>> // into an infinite loop.
>> assert ((!IsLegalizingCall ||
>> Node->getOpcode() != ISD::CALL ||
>> - Tmp3.Val->getOpcode() != ISD::CALLSEQ_END) &&
>> + Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
>> "Nested CALLSEQ_START..CALLSEQ_END not supported.");
>>
>> // The number of incoming and outgoing values should match;
>> unless the final
>> // outgoing value is a flag.
>> - assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues()
>> ||
>> - (Tmp3.Val->getNumValues() == Result.Val->getNumValues()
>> + 1 &&
>> - Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
>> + assert((Tmp3.getNode()->getNumValues() == Result.getNode()-
>>> getNumValues() ||
>> + (Tmp3.getNode()->getNumValues() == Result.getNode()-
>>> getNumValues() + 1 &&
>> + Tmp3.getNode()->getValueType(Tmp3.getNode()-
>>> getNumValues() - 1) ==
>> MVT::Flag)) &&
>> "Lowering call/formal_arguments produced unexpected #
>> results!");
>>
>> // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values,
>> make sure to
>> // remember that we legalized all of them, so it doesn't get
>> relegalized.
>> - for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; +
>> +i) {
>> - if (Tmp3.Val->getValueType(i) == MVT::Flag)
>> + for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i !=
>> e; ++i) {
>> + if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
>> continue;
>> Tmp1 = LegalizeOp(Tmp3.getValue(i));
>> if (Op.getResNo() == i)
>> @@ -1394,13 +1394,13 @@
>> default: assert(0 && "This action is not supported yet!");
>> case TargetLowering::Custom:
>> Tmp3 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp3.Val) {
>> + if (Tmp3.getNode()) {
>> Result = Tmp3;
>> break;
>> }
>> // FALLTHROUGH
>> case TargetLowering::Expand:
>> - Result = ExpandBUILD_VECTOR(Result.Val);
>> + Result = ExpandBUILD_VECTOR(Result.getNode());
>> break;
>> }
>> break;
>> @@ -1425,7 +1425,7 @@
>> break;
>> case TargetLowering::Custom:
>> Tmp4 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp4.Val) {
>> + if (Tmp4.getNode()) {
>> Result = Tmp4;
>> break;
>> }
>> @@ -1485,7 +1485,7 @@
>> break;
>> case TargetLowering::Custom:
>> Tmp3 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp3.Val) {
>> + if (Tmp3.getNode()) {
>> Result = Tmp3;
>> break;
>> }
>> @@ -1509,7 +1509,7 @@
>> break;
>> case TargetLowering::Custom:
>> Tmp3 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp3.Val) {
>> + if (Tmp3.getNode()) {
>> Result = Tmp3;
>> break;
>> }
>> @@ -1550,7 +1550,7 @@
>>
>> // Convert the shuffle mask to the right # elements.
>> Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
>> - assert(Tmp3.Val && "Shuffle not legal?");
>> + assert(Tmp3.getNode() && "Shuffle not legal?");
>> Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2,
>> Tmp3);
>> Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
>> break;
>> @@ -1580,7 +1580,7 @@
>> // are inserted *before* the CALLSEQ_START.
>> {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
>> for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
>> - LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
>> + LegalizeAllNodesNotLeadingTo(CallEnd-
>>> getOperand(i).getNode(), Node,
>> NodesLeadingTo);
>> }
>>
>> @@ -1624,7 +1624,7 @@
>> case ISD::CALLSEQ_END:
>> // If the CALLSEQ_START node hasn't been legalized first,
>> legalize it. This
>> // will cause this node to be legalized as well as handling
>> libcalls right.
>> - if (LastCALLSEQ_END.Val != Node) {
>> + if (LastCALLSEQ_END.getNode() != Node) {
>> LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
>> DenseMap<SDValue, SDValue>::iterator I =
>> LegalizedNodes.find(Op);
>> assert(I != LegalizedNodes.end() &&
>> @@ -1708,7 +1708,7 @@
>> }
>> case TargetLowering::Custom:
>> Tmp3 = TLI.LowerOperation(Tmp1, DAG);
>> - if (Tmp3.Val) {
>> + if (Tmp3.getNode()) {
>> Tmp1 = LegalizeOp(Tmp3);
>> Tmp2 = LegalizeOp(Tmp3.getValue(1));
>> }
>> @@ -1797,7 +1797,7 @@
>> case TargetLowering::Legal: break;
>> case TargetLowering::Custom:
>> Tmp1 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp1.Val) Result = Tmp1;
>> + if (Tmp1.getNode()) Result = Tmp1;
>> break;
>> case TargetLowering::Expand: {
>> SDValue Chain = Result.getOperand(0);
>> @@ -1866,7 +1866,7 @@
>> case TargetLowering::Legal: break;
>> case TargetLowering::Custom:
>> Tmp1 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp1.Val) Result = Tmp1;
>> + if (Tmp1.getNode()) Result = Tmp1;
>> break;
>> case TargetLowering::Expand:
>> // Expand brcond's setcc into its constituent parts and create
>> a BR_CC
>> @@ -1899,7 +1899,7 @@
>> // If we didn't get both a LHS and RHS back from
>> LegalizeSetCCOperands,
>> // the LHS is a legal SETCC itself. In this case, we need to
>> compare
>> // the result against zero to select between true and false
>> values.
>> - if (Tmp3.Val == 0) {
>> + if (Tmp3.getNode() == 0) {
>> Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
>> Tmp4 = DAG.getCondCode(ISD::SETNE);
>> }
>> @@ -1912,7 +1912,7 @@
>> case TargetLowering::Legal: break;
>> case TargetLowering::Custom:
>> Tmp4 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp4.Val) Result = Tmp4;
>> + if (Tmp4.getNode()) Result = Tmp4;
>> break;
>> }
>> break;
>> @@ -1937,7 +1937,7 @@
>> unsigned ABIAlignment = TLI.getTargetData()->
>> getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
>> if (LD->getAlignment() < ABIAlignment){
>> - Result =
>> ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
>> + Result =
>> ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
>> TLI);
>> Tmp3 = Result.getOperand(0);
>> Tmp4 = Result.getOperand(1);
>> @@ -1948,7 +1948,7 @@
>> break;
>> case TargetLowering::Custom:
>> Tmp1 = TLI.LowerOperation(Tmp3, DAG);
>> - if (Tmp1.Val) {
>> + if (Tmp1.getNode()) {
>> Tmp3 = LegalizeOp(Tmp1);
>> Tmp4 = LegalizeOp(Tmp1.getValue(1));
>> }
>> @@ -2105,7 +2105,7 @@
>>
>> if (isCustom) {
>> Tmp3 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp3.Val) {
>> + if (Tmp3.getNode()) {
>> Tmp1 = LegalizeOp(Tmp3);
>> Tmp2 = LegalizeOp(Tmp3.getValue(1));
>> }
>> @@ -2116,7 +2116,7 @@
>> unsigned ABIAlignment = TLI.getTargetData()->
>> getABITypeAlignment(LD-
>>> getMemoryVT().getTypeForMVT());
>> if (LD->getAlignment() < ABIAlignment){
>> - Result =
>> ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
>> + Result =
>> ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
>> TLI);
>> Tmp1 = Result.getOperand(0);
>> Tmp2 = Result.getOperand(1);
>> @@ -2244,13 +2244,13 @@
>> if (TLI.isBigEndian())
>> std::swap(Lo, Hi);
>>
>> - if (Hi.Val)
>> + if (Hi.getNode())
>> Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo,
>> Tmp3, Hi,Tmp3);
>> else
>> Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo,
>> Tmp3);
>> Result = LegalizeOp(Result);
>> } else {
>> - SDNode *InVal = Tmp2.Val;
>> + SDNode *InVal = Tmp2.getNode();
>> int InIx = Tmp2.getResNo();
>> unsigned NumElems = InVal-
>>> getValueType(InIx).getVectorNumElements();
>> MVT EVT = InVal->getValueType(InIx).getVectorElementType();
>> @@ -2310,7 +2310,7 @@
>> ExpandOp(Node->getOperand(i), Lo, Hi);
>> NewValues.push_back(Lo);
>> NewValues.push_back(Node->getOperand(i+1));
>> - if (Hi.Val) {
>> + if (Hi.getNode()) {
>> NewValues.push_back(Hi);
>> NewValues.push_back(Node->getOperand(i+1));
>> }
>> @@ -2335,7 +2335,7 @@
>> case TargetLowering::Legal: break;
>> case TargetLowering::Custom:
>> Tmp1 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp1.Val) Result = Tmp1;
>> + if (Tmp1.getNode()) Result = Tmp1;
>> break;
>> }
>> }
>> @@ -2411,13 +2411,13 @@
>> unsigned ABIAlignment = TLI.getTargetData()->
>> getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
>> if (ST->getAlignment() < ABIAlignment)
>> - Result =
>> ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
>> + Result =
>> ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
>> TLI);
>> }
>> break;
>> case TargetLowering::Custom:
>> Tmp1 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp1.Val) Result = Tmp1;
>> + if (Tmp1.getNode()) Result = Tmp1;
>> break;
>> case TargetLowering::Promote:
>> assert(VT.isVector() && "Unknown legal promote case!");
>> @@ -2446,7 +2446,7 @@
>> // the product of the element size in bytes, and the number
>> of elements
>> // in the high half of the vector.
>> if (ST->getValue().getValueType().isVector()) {
>> - SDNode *InVal = ST->getValue().Val;
>> + SDNode *InVal = ST->getValue().getNode();
>> int InIx = ST->getValue().getResNo();
>> MVT InVT = InVal->getValueType(InIx);
>> unsigned NumElems = InVT.getVectorNumElements();
>> @@ -2473,12 +2473,12 @@
>> break;
>> } else {
>> SplitVectorOp(ST->getValue(), Lo, Hi);
>> - IncrementSize = Lo.Val-
>>> getValueType(0).getVectorNumElements() *
>> + IncrementSize = Lo.getNode()-
>>> getValueType(0).getVectorNumElements() *
>> EVT.getSizeInBits()/8;
>> }
>> } else {
>> ExpandOp(ST->getValue(), Lo, Hi);
>> - IncrementSize = Hi.Val ?
>> Hi.getValueType().getSizeInBits()/8 : 0;
>> + IncrementSize = Hi.getNode() ?
>> Hi.getValueType().getSizeInBits()/8 : 0;
>>
>> if (TLI.isBigEndian())
>> std::swap(Lo, Hi);
>> @@ -2487,7 +2487,7 @@
>> Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
>> SVOffset, isVolatile, Alignment);
>>
>> - if (Hi.Val == NULL) {
>> + if (Hi.getNode() == NULL) {
>> // Must be int <-> float one-to-one expansion.
>> Result = Lo;
>> break;
>> @@ -2598,7 +2598,7 @@
>> unsigned ABIAlignment = TLI.getTargetData()->
>> getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
>> if (ST->getAlignment() < ABIAlignment)
>> - Result =
>> ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
>> + Result =
>> ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
>> TLI);
>> }
>> break;
>> @@ -2632,7 +2632,7 @@
>> case TargetLowering::Legal: break;
>> case TargetLowering::Custom:
>> Tmp3 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp3.Val) {
>> + if (Tmp3.getNode()) {
>> Tmp1 = LegalizeOp(Tmp3);
>> Tmp2 = LegalizeOp(Tmp3.getValue(1));
>> }
>> @@ -2667,7 +2667,7 @@
>> case TargetLowering::Legal: break;
>> case TargetLowering::Custom:
>> Tmp1 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp1.Val) Result = Tmp1;
>> + if (Tmp1.getNode()) Result = Tmp1;
>> break;
>> case TargetLowering::Expand:
>> // Expand to CopyToReg if the target set
>> @@ -2730,7 +2730,7 @@
>> case TargetLowering::Legal: break;
>> case TargetLowering::Custom: {
>> Tmp1 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp1.Val) Result = Tmp1;
>> + if (Tmp1.getNode()) Result = Tmp1;
>> break;
>> }
>> case TargetLowering::Expand:
>> @@ -2784,7 +2784,7 @@
>> // If we didn't get both a LHS and RHS back from
>> LegalizeSetCCOperands,
>> // the LHS is a legal SETCC itself. In this case, we need to
>> compare
>> // the result against zero to select between true and false
>> values.
>> - if (Tmp2.Val == 0) {
>> + if (Tmp2.getNode() == 0) {
>> Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
>> CC = DAG.getCondCode(ISD::SETNE);
>> }
>> @@ -2796,7 +2796,7 @@
>> case TargetLowering::Legal: break;
>> case TargetLowering::Custom:
>> Tmp1 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp1.Val) Result = Tmp1;
>> + if (Tmp1.getNode()) Result = Tmp1;
>> break;
>> }
>> break;
>> @@ -2810,7 +2810,7 @@
>> // If we had to Expand the SetCC operands into a SELECT node,
>> then it may
>> // not always be possible to return a true LHS & RHS. In this
>> case, just
>> // return the value we legalized, returned in the LHS
>> - if (Tmp2.Val == 0) {
>> + if (Tmp2.getNode() == 0) {
>> Result = Tmp1;
>> break;
>> }
>> @@ -2824,7 +2824,7 @@
>> Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
>> if (isCustom) {
>> Tmp4 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp4.Val) Result = Tmp4;
>> + if (Tmp4.getNode()) Result = Tmp4;
>> }
>> break;
>> case TargetLowering::Promote: {
>> @@ -2882,7 +2882,7 @@
>> case TargetLowering::Legal: break;
>> case TargetLowering::Custom:
>> Tmp1 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp1.Val) Result = Tmp1;
>> + if (Tmp1.getNode()) Result = Tmp1;
>> break;
>> }
>> break;
>> @@ -2906,7 +2906,7 @@
>> case TargetLowering::Legal: break;
>> case TargetLowering::Custom:
>> Tmp1 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp1.Val) {
>> + if (Tmp1.getNode()) {
>> SDValue Tmp2, RetVal(0, 0);
>> for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
>> Tmp2 = LegalizeOp(Tmp1.getValue(i));
>> @@ -2914,7 +2914,7 @@
>> if (i == Op.getResNo())
>> RetVal = Tmp2;
>> }
>> - assert(RetVal.Val && "Illegal result number");
>> + assert(RetVal.getNode() && "Illegal result number");
>> return RetVal;
>> }
>> break;
>> @@ -2974,7 +2974,7 @@
>> case TargetLowering::Legal: break;
>> case TargetLowering::Custom:
>> Tmp1 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp1.Val) {
>> + if (Tmp1.getNode()) {
>> Result = Tmp1;
>> break;
>> }
>> @@ -3004,28 +3004,28 @@
>> OpToUse = ISD::UMUL_LOHI;
>> }
>> if (OpToUse) {
>> - Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1,
>> Tmp2).Val, 0);
>> + Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1,
>> Tmp2).getNode(), 0);
>> break;
>> }
>> }
>> if (Node->getOpcode() == ISD::MULHS &&
>> TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
>> - Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1,
>> Tmp2).Val, 1);
>> + Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1,
>> Tmp2).getNode(), 1);
>> break;
>> }
>> if (Node->getOpcode() == ISD::MULHU &&
>> TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
>> - Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1,
>> Tmp2).Val, 1);
>> + Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1,
>> Tmp2).getNode(), 1);
>> break;
>> }
>> if (Node->getOpcode() == ISD::SDIV &&
>> TLI.isOperationLegal(ISD::SDIVREM, VT)) {
>> - Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1,
>> Tmp2).Val, 0);
>> + Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1,
>> Tmp2).getNode(), 0);
>> break;
>> }
>> if (Node->getOpcode() == ISD::UDIV &&
>> TLI.isOperationLegal(ISD::UDIVREM, VT)) {
>> - Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1,
>> Tmp2).Val, 0);
>> + Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1,
>> Tmp2).getNode(), 0);
>> break;
>> }
>>
>> @@ -3113,7 +3113,7 @@
>> default: assert(0 && "Operation not supported");
>> case TargetLowering::Custom:
>> Tmp1 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp1.Val) Result = Tmp1;
>> + if (Tmp1.getNode()) Result = Tmp1;
>> break;
>> case TargetLowering::Legal: break;
>> case TargetLowering::Expand: {
>> @@ -3216,7 +3216,7 @@
>> Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
>> if (isCustom) {
>> Tmp1 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp1.Val) Result = Tmp1;
>> + if (Tmp1.getNode()) Result = Tmp1;
>> }
>> break;
>> case TargetLowering::Expand: {
>> @@ -3228,12 +3228,12 @@
>> SDVTList VTs = DAG.getVTList(VT, VT);
>> if (Node->getOpcode() == ISD::SREM &&
>> TLI.isOperationLegal(ISD::SDIVREM, VT)) {
>> - Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1,
>> Tmp2).Val, 1);
>> + Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1,
>> Tmp2).getNode(), 1);
>> break;
>> }
>> if (Node->getOpcode() == ISD::UREM &&
>> TLI.isOperationLegal(ISD::UDIVREM, VT)) {
>> - Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1,
>> Tmp2).Val, 1);
>> + Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1,
>> Tmp2).getNode(), 1);
>> break;
>> }
>>
>> @@ -3288,7 +3288,7 @@
>>
>> if (isCustom) {
>> Tmp2 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp2.Val) {
>> + if (Tmp2.getNode()) {
>> Result = LegalizeOp(Tmp2);
>> Tmp1 = LegalizeOp(Tmp2.getValue(1));
>> }
>> @@ -3332,7 +3332,7 @@
>> Node->getOperand(3), Node-
>>> getOperand(4));
>> if (isCustom) {
>> Tmp1 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp1.Val) Result = Tmp1;
>> + if (Tmp1.getNode()) Result = Tmp1;
>> }
>> break;
>> case TargetLowering::Expand:
>> @@ -3359,7 +3359,7 @@
>> Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node-
>>> getOperand(2));
>> if (isCustom) {
>> Tmp1 = TLI.LowerOperation(Tmp1, DAG);
>> - if (Tmp1.Val) Result = Tmp1;
>> + if (Tmp1.getNode()) Result = Tmp1;
>> }
>> break;
>> case TargetLowering::Expand:
>> @@ -3379,7 +3379,7 @@
>> case TargetLowering::Legal: break;
>> case TargetLowering::Custom:
>> Tmp1 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp1.Val) Result = Tmp1;
>> + if (Tmp1.getNode()) Result = Tmp1;
>> break;
>> }
>> break;
>> @@ -3397,7 +3397,7 @@
>> break;
>> case TargetLowering::Custom:
>> Tmp1 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp1.Val) Result = Tmp1;
>> + if (Tmp1.getNode()) Result = Tmp1;
>> break;
>> case TargetLowering::Promote:
>> assert(0 && "Do not know how to promote ROTL/ROTR");
>> @@ -3444,7 +3444,7 @@
>> if (TLI.getOperationAction(Node->getOpcode(), Node-
>>> getValueType(0)) ==
>> TargetLowering::Custom) {
>> Tmp1 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp1.Val) {
>> + if (Tmp1.getNode()) {
>> Result = Tmp1;
>> }
>> }
>> @@ -3505,7 +3505,7 @@
>> Result = DAG.UpdateNodeOperands(Result, Tmp1);
>> if (isCustom) {
>> Tmp1 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp1.Val) Result = Tmp1;
>> + if (Tmp1.getNode()) Result = Tmp1;
>> }
>> break;
>> case TargetLowering::Expand:
>> @@ -3609,7 +3609,7 @@
>> } else if (Op.getOperand(0).getValueType().isVector()) {
>> // The input has to be a vector type, we have to either
>> scalarize it, pack
>> // it, or convert it based on whether the input vector type is
>> legal.
>> - SDNode *InVal = Node->getOperand(0).Val;
>> + SDNode *InVal = Node->getOperand(0).getNode();
>> int InIx = Node->getOperand(0).getResNo();
>> unsigned NumElems = InVal-
>>> getValueType(InIx).getVectorNumElements();
>> MVT EVT = InVal->getValueType(InIx).getVectorElementType();
>> @@ -3690,7 +3690,7 @@
>> Result = DAG.UpdateNodeOperands(Result, Tmp1);
>> if (isCustom) {
>> Tmp1 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp1.Val) Result = Tmp1;
>> + if (Tmp1.getNode()) Result = Tmp1;
>> }
>> break;
>> case TargetLowering::Promote:
>> @@ -3832,7 +3832,7 @@
>> if (TLI.getOperationAction(Node->getOpcode(), Node-
>>> getValueType(0)) ==
>> TargetLowering::Custom) {
>> Tmp1 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp1.Val) Result = Tmp1;
>> + if (Tmp1.getNode()) Result = Tmp1;
>> }
>> break;
>> case Promote:
>> @@ -3904,7 +3904,7 @@
>> Result = DAG.UpdateNodeOperands(Result, Ops, 6);
>> // The only option for this node is to custom lower it.
>> Result = TLI.LowerOperation(Result, DAG);
>> - assert(Result.Val && "Should always custom lower!");
>> + assert(Result.getNode() && "Should always custom lower!");
>>
>> // Since trampoline produces two values, make sure to remember
>> that we
>> // legalized both of them.
>> @@ -3920,7 +3920,7 @@
>> default: assert(0 && "This action not supported for this op
>> yet!");
>> case TargetLowering::Custom:
>> Result = TLI.LowerOperation(Op, DAG);
>> - if (Result.Val) break;
>> + if (Result.getNode()) break;
>> // Fall Thru
>> case TargetLowering::Legal:
>> // If this operation is not supported, lower it to constant 1
>> @@ -3939,7 +3939,7 @@
>> break;
>> case TargetLowering::Custom:
>> Result = TLI.LowerOperation(Op, DAG);
>> - if (Result.Val) break;
>> + if (Result.getNode()) break;
>> // Fall Thru
>> case TargetLowering::Expand:
>> // If this operation is not supported, lower it to 'abort()'
>> call
>> @@ -3984,7 +3984,7 @@
>>
>> SDValue Tmp1, Tmp2, Tmp3;
>> SDValue Result;
>> - SDNode *Node = Op.Val;
>> + SDNode *Node = Op.getNode();
>>
>> DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
>> if (I != PromotedNodes.end()) return I->second;
>> @@ -4461,7 +4461,7 @@
>> break;
>> }
>>
>> - assert(Result.Val && "Didn't set a result!");
>> + assert(Result.getNode() && "Didn't set a result!");
>>
>> // Make sure the result is itself legal.
>> Result = LegalizeOp(Result);
>> @@ -4491,7 +4491,7 @@
>> Vec = LegalizeOp(Vec);
>> Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
>> SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
>> - if (Tmp3.Val)
>> + if (Tmp3.getNode())
>> return Tmp3;
>> break;
>> }
>> @@ -4697,14 +4697,14 @@
>>
>> SDValue Dummy;
>> SDValue Ops[2] = { LHS, RHS };
>> - Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).Val,
>> + Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops,
>> 2).getNode(),
>> false /*sign irrelevant*/, Dummy);
>> Tmp2 = DAG.getConstant(0, MVT::i32);
>> CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
>> if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
>> Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1),
>> Tmp1, Tmp2,
>> CC);
>> - LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).Val,
>> + LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops,
>> 2).getNode(),
>> false /*sign irrelevant*/, Dummy);
>> Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS),
>> LHS, Tmp2,
>> DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
>> @@ -4791,16 +4791,16 @@
>> TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false,
>> true, NULL);
>> Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo,
>> RHSLo,
>> LowCC, false, DagCombineInfo);
>> - if (!Tmp1.Val)
>> + if (!Tmp1.getNode())
>> Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo,
>> RHSLo, LowCC);
>> Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi,
>> RHSHi,
>> CCCode, false, DagCombineInfo);
>> - if (!Tmp2.Val)
>> + if (!Tmp2.getNode())
>> Tmp2 = DAG.getNode(ISD::SETCC,
>> TLI.getSetCCResultType(LHSHi), LHSHi,
>> RHSHi,CC);
>>
>> - ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
>> - ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
>> + ConstantSDNode *Tmp1C =
>> dyn_cast<ConstantSDNode>(Tmp1.getNode());
>> + ConstantSDNode *Tmp2C =
>> dyn_cast<ConstantSDNode>(Tmp2.getNode());
>> if ((Tmp1C && Tmp1C->isNullValue()) ||
>> (Tmp2C && Tmp2C->isNullValue() &&
>> (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
>> @@ -4816,7 +4816,7 @@
>> } else {
>> Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi),
>> LHSHi, RHSHi,
>> ISD::SETEQ, false, DagCombineInfo);
>> - if (!Result.Val)
>> + if (!Result.getNode())
>> Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi,
>> RHSHi,
>> ISD::SETEQ);
>> Result = LegalizeOp(DAG.getNode(ISD::SELECT,
>> Tmp1.getValueType(),
>> @@ -4958,7 +4958,7 @@
>> PseudoSourceValue::getConstantPool(), 0);
>> }
>>
>> - if (SplatValue.Val) { // Splat of one value?
>> + if (SplatValue.getNode()) { // Splat of one value?
>> // Build the shuffle constant vector: <0, 0, 0, 0>
>> MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
>> SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
>> @@ -5095,7 +5095,7 @@
>> unsigned NVTBits = NVT.getSizeInBits();
>>
>> // Handle the case when Amt is an immediate.
>> - if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
>> + if (ConstantSDNode *CN =
>> dyn_cast<ConstantSDNode>(Amt.getNode())) {
>> unsigned Cst = CN->getValue();
>> // Expand the incoming operand to be shifted, so that we have
>> its parts
>> SDValue InL, InH;
>> @@ -5292,14 +5292,14 @@
>> // FALLTHROUGH
>> case TargetLowering::Legal:
>> Tmp1 = LegalizeOp(Op);
>> - if (Result.Val)
>> + if (Result.getNode())
>> Result = DAG.UpdateNodeOperands(Result, Tmp1);
>> else
>> Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP :
>> ISD::UINT_TO_FP,
>> DestTy, Tmp1);
>> if (isCustom) {
>> Tmp1 = TLI.LowerOperation(Result, DAG);
>> - if (Tmp1.Val) Result = Tmp1;
>> + if (Tmp1.getNode()) Result = Tmp1;
>> }
>> break;
>> case TargetLowering::Expand:
>> @@ -5322,7 +5322,7 @@
>> Tmp1 = DAG.getZeroExtendInReg(Tmp1,
>> Op.getValueType());
>> }
>> - if (Result.Val)
>> + if (Result.getNode())
>> Result = DAG.UpdateNodeOperands(Result, Tmp1);
>> else
>> Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP :
>> ISD::UINT_TO_FP,
>> @@ -5427,7 +5427,7 @@
>> case TargetLowering::Custom: {
>> SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP,
>> DestTy,
>> Source), DAG);
>> - if (NV.Val)
>> + if (NV.getNode())
>> return LegalizeOp(NV);
>> break; // The target decided this was legal after all
>> }
>> @@ -5448,8 +5448,8 @@
>>
>> Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
>> SDValue HiPart;
>> - SDValue Result = ExpandLibCall(LC, Source.Val, isSigned, HiPart);
>> - if (Result.getValueType() != DestTy && HiPart.Val)
>> + SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned,
>> HiPart);
>> + if (Result.getValueType() != DestTy && HiPart.getNode())
>> Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
>> return Result;
>> }
>> @@ -5665,8 +5665,8 @@
>> // the target lowering hooks to expand it. Just keep the low part
>> of the
>> // expanded operation, we know that we're truncating anyway.
>> if (getTypeAction(NewOutTy) == Expand) {
>> - Operation = SDValue(TLI.ReplaceNodeResults(Operation.Val, DAG),
>> 0);
>> - assert(Operation.Val && "Didn't return anything");
>> + Operation = SDValue(TLI.ReplaceNodeResults(Operation.getNode(),
>> DAG), 0);
>> + assert(Operation.getNode() && "Didn't return anything");
>> }
>>
>> // Truncate the result of the extended FP_TO_*INT operation to the
>> desired
>> @@ -5794,7 +5794,7 @@
>> void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue
>> &Hi){
>> MVT VT = Op.getValueType();
>> MVT NVT = TLI.getTypeToTransformTo(VT);
>> - SDNode *Node = Op.Val;
>> + SDNode *Node = Op.getNode();
>> assert(getTypeAction(VT) == Expand && "Not an expanded type!");
>> assert(((NVT.isInteger() && NVT.bitsLT(VT)) ||
>> VT.isFloatingPoint() ||
>> VT.isVector()) && "Cannot expand to FP value or to larger
>> int value!");
>> @@ -5820,9 +5820,9 @@
>> Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
>> SDValue Result = TLI.LowerOperation(
>> DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)),
>> DAG);
>> - assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
>> - Lo = Result.Val->getOperand(0);
>> - Hi = Result.Val->getOperand(1);
>> + assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
>> + Lo = Result.getNode()->getOperand(0);
>> + Hi = Result.getNode()->getOperand(1);
>> break;
>> }
>> // fall through
>> @@ -6145,7 +6145,7 @@
>> }
>>
>> // Turn this into a load/store pair by default.
>> - if (Tmp.Val == 0)
>> + if (Tmp.getNode() == 0)
>> Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
>>
>> ExpandOp(Tmp, Lo, Hi);
>> @@ -6157,7 +6157,7 @@
>> TargetLowering::Custom &&
>> "Must custom expand ReadCycleCounter");
>> SDValue Tmp = TLI.LowerOperation(Op, DAG);
>> - assert(Tmp.Val && "Node must be custom expanded!");
>> + assert(Tmp.getNode() && "Node must be custom expanded!");
>> ExpandOp(Tmp.getValue(0), Lo, Hi);
>> AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized
>> the chain.
>> LegalizeOp(Tmp.getValue(1)));
>> @@ -6170,7 +6170,7 @@
>> case ISD::ATOMIC_CMP_SWAP_32:
>> case ISD::ATOMIC_CMP_SWAP_64: {
>> SDValue Tmp = TLI.LowerOperation(Op, DAG);
>> - assert(Tmp.Val && "Node must be custom expanded!");
>> + assert(Tmp.getNode() && "Node must be custom expanded!");
>> ExpandOp(Tmp.getValue(0), Lo, Hi);
>> AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized
>> the chain.
>> LegalizeOp(Tmp.getValue(1)));
>> @@ -6194,7 +6194,7 @@
>>
>> // Now that the custom expander is done, expand the result,
>> which is still
>> // VT.
>> - if (Op.Val) {
>> + if (Op.getNode()) {
>> ExpandOp(Op, Lo, Hi);
>> break;
>> }
>> @@ -6219,7 +6219,7 @@
>> Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op),
>> DAG);
>>
>> // Now that the custom expander is done, expand the result.
>> - if (Op.Val) {
>> + if (Op.getNode()) {
>> ExpandOp(Op, Lo, Hi);
>> break;
>> }
>> @@ -6238,7 +6238,7 @@
>> if (TLI.getOperationAction(ISD::SHL, VT) ==
>> TargetLowering::Custom) {
>> SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0),
>> ShiftAmt);
>> Op = TLI.LowerOperation(Op, DAG);
>> - if (Op.Val) {
>> + if (Op.getNode()) {
>> // Now that the custom expander is done, expand the result,
>> which is
>> // still VT.
>> ExpandOp(Op, Lo, Hi);
>> @@ -6288,7 +6288,7 @@
>> if (TLI.getOperationAction(ISD::SRA, VT) ==
>> TargetLowering::Custom) {
>> SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0),
>> ShiftAmt);
>> Op = TLI.LowerOperation(Op, DAG);
>> - if (Op.Val) {
>> + if (Op.getNode()) {
>> // Now that the custom expander is done, expand the result,
>> which is
>> // still VT.
>> ExpandOp(Op, Lo, Hi);
>> @@ -6320,7 +6320,7 @@
>> if (TLI.getOperationAction(ISD::SRL, VT) ==
>> TargetLowering::Custom) {
>> SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0),
>> ShiftAmt);
>> Op = TLI.LowerOperation(Op, DAG);
>> - if (Op.Val) {
>> + if (Op.getNode()) {
>> // Now that the custom expander is done, expand the result,
>> which is
>> // still VT.
>> ExpandOp(Op, Lo, Hi);
>> @@ -6352,7 +6352,7 @@
>> if (TLI.getOperationAction(Node->getOpcode(), VT) ==
>> TargetLowering::Custom) {
>> SDValue Result = TLI.LowerOperation(Op, DAG);
>> - if (Result.Val) {
>> + if (Result.getNode()) {
>> ExpandOp(Result, Lo, Hi);
>> break;
>> }
>> @@ -6425,7 +6425,7 @@
>> // If the target wants to custom expand this, let them.
>> if (TLI.getOperationAction(ISD::MUL, VT) ==
>> TargetLowering::Custom) {
>> SDValue New = TLI.LowerOperation(Op, DAG);
>> - if (New.Val) {
>> + if (New.getNode()) {
>> ExpandOp(New, Lo, Hi);
>> break;
>> }
>> @@ -6450,7 +6450,7 @@
>> if (HasUMUL_LOHI) {
>> // We can emit a umul_lohi.
>> Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT),
>> LL, RL);
>> - Hi = SDValue(Lo.Val, 1);
>> + Hi = SDValue(Lo.getNode(), 1);
>> break;
>> }
>> if (HasMULHU) {
>> @@ -6465,7 +6465,7 @@
>> if (HasSMUL_LOHI) {
>> // We can emit a smul_lohi.
>> Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT),
>> LL, RL);
>> - Hi = SDValue(Lo.Val, 1);
>> + Hi = SDValue(Lo.getNode(), 1);
>> break;
>> }
>> if (HasMULHS) {
>> @@ -6678,7 +6678,7 @@
>> ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
>> DAG.getValueType(SrcVT))
>> : DAG.getZeroExtendInReg(Tmp, SrcVT);
>> - Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
>> + Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
>> SrcVT = Node->getOperand(0).getValueType();
>> }
>>
>> @@ -6739,7 +6739,7 @@
>> // is a type that requires multi-step expansion.
>> if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
>> Lo = LegalizeOp(Lo);
>> - if (Hi.Val)
>> + if (Hi.getNode())
>> // Don't legalize the high part if it is expanded to a single
>> node.
>> Hi = LegalizeOp(Hi);
>> }
>> @@ -6755,7 +6755,7 @@
>> void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
>> SDValue &Hi) {
>> assert(Op.getValueType().isVector() && "Cannot split non-vector
>> type!");
>> - SDNode *Node = Op.Val;
>> + SDNode *Node = Op.getNode();
>> unsigned NumElements = Op.getValueType().getVectorNumElements();
>> assert(NumElements > 1 && "Cannot split a single element vector!");
>>
>> @@ -7033,7 +7033,7 @@
>> unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
>>
>> Op.getValueType().getTypeForMVT());
>> SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(),
>> LdAlign);
>> - int FI = cast<FrameIndexSDNode>(Ptr.Val)->getIndex();
>> + int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
>>
>> SDValue St = DAG.getStore(DAG.getEntryNode(),
>> InOp, Ptr,
>> @@ -7061,7 +7061,7 @@
>> /// scalar (e.g. f32) value.
>> SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
>> assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp
>> invocation!");
>> - SDNode *Node = Op.Val;
>> + SDNode *Node = Op.getNode();
>> MVT NewVT = Op.getValueType().getVectorElementType();
>> assert(Op.getValueType().getVectorNumElements() == 1);
>>
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
>> (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Thu
>> Aug 28 16:40:38 2008
>> @@ -76,7 +76,7 @@
>> }
>>
>> // If R is null, the sub-method took care of registering the result.
>> - if (R.Val)
>> + if (R.getNode())
>> SetSoftenedFloat(SDValue(N, ResNo), R);
>> }
>>
>> @@ -311,11 +311,11 @@
>> }
>>
>> // If the result is null, the sub-method took care of registering
>> results etc.
>> - if (!Res.Val) return false;
>> + if (!Res.getNode()) return false;
>>
>> // If the result is N, the sub-method updated N in place. Check
>> to see if any
>> // operands are new, and if so, mark them.
>> - if (Res.Val == N) {
>> + if (Res.getNode() == N) {
>> // Mark N as new and remark N and its operands. This allows us
>> to correctly
>> // revisit N if it needs another step of promotion and allows us
>> to visit
>> // any new operands to N.
>> @@ -438,7 +438,7 @@
>>
>> // If SoftenSetCCOperands returned a scalar, we need to compare
>> the result
>> // against zero to select between true and false values.
>> - if (NewRHS.Val == 0) {
>> + if (NewRHS.getNode() == 0) {
>> NewRHS = DAG.getConstant(0, NewLHS.getValueType());
>> CCCode = ISD::SETNE;
>> }
>> @@ -472,7 +472,7 @@
>>
>> // If SoftenSetCCOperands returned a scalar, we need to compare
>> the result
>> // against zero to select between true and false values.
>> - if (NewRHS.Val == 0) {
>> + if (NewRHS.getNode() == 0) {
>> NewRHS = DAG.getConstant(0, NewLHS.getValueType());
>> CCCode = ISD::SETNE;
>> }
>> @@ -489,7 +489,7 @@
>> SoftenSetCCOperands(NewLHS, NewRHS, CCCode);
>>
>> // If SoftenSetCCOperands returned a scalar, use it.
>> - if (NewRHS.Val == 0) {
>> + if (NewRHS.getNode() == 0) {
>> assert(NewLHS.getValueType() == N->getValueType(0) &&
>> "Unexpected setcc expansion!");
>> return NewLHS;
>> @@ -577,7 +577,7 @@
>> }
>>
>> // If Lo/Hi is null, the sub-method took care of registering
>> results etc.
>> - if (Lo.Val)
>> + if (Lo.getNode())
>> SetExpandedFloat(SDValue(N, ResNo), Lo, Hi);
>> }
>>
>> @@ -603,7 +603,7 @@
>> RTLIB::ADD_PPCF128),
>> N->getValueType(0), Ops, 2,
>> false);
>> - assert(Call.Val->getOpcode() == ISD::BUILD_PAIR && "Call lowered
>> wrongly!");
>> + assert(Call.getNode()->getOpcode() == ISD::BUILD_PAIR && "Call
>> lowered wrongly!");
>> Lo = Call.getOperand(0); Hi = Call.getOperand(1);
>> }
>>
>> @@ -630,7 +630,7 @@
>> RTLIB::DIV_PPCF128),
>> N->getValueType(0), Ops, 2,
>> false);
>> - assert(Call.Val->getOpcode() == ISD::BUILD_PAIR && "Call lowered
>> wrongly!");
>> + assert(Call.getNode()->getOpcode() == ISD::BUILD_PAIR && "Call
>> lowered wrongly!");
>> Lo = Call.getOperand(0); Hi = Call.getOperand(1);
>> }
>>
>> @@ -644,7 +644,7 @@
>> RTLIB::MUL_PPCF128),
>> N->getValueType(0), Ops, 2,
>> false);
>> - assert(Call.Val->getOpcode() == ISD::BUILD_PAIR && "Call lowered
>> wrongly!");
>> + assert(Call.getNode()->getOpcode() == ISD::BUILD_PAIR && "Call
>> lowered wrongly!");
>> Lo = Call.getOperand(0); Hi = Call.getOperand(1);
>> }
>>
>> @@ -672,7 +672,7 @@
>> RTLIB::SUB_PPCF128),
>> N->getValueType(0), Ops, 2,
>> false);
>> - assert(Call.Val->getOpcode() == ISD::BUILD_PAIR && "Call lowered
>> wrongly!");
>> + assert(Call.getNode()->getOpcode() == ISD::BUILD_PAIR && "Call
>> lowered wrongly!");
>> Lo = Call.getOperand(0); Hi = Call.getOperand(1);
>> }
>>
>> @@ -734,7 +734,7 @@
>> assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XINT_TO_FP!");
>>
>> Hi = MakeLibCall(LC, VT, &Src, 1, true);
>> - assert(Hi.Val->getOpcode() == ISD::BUILD_PAIR && "Call lowered
>> wrongly!");
>> + assert(Hi.getNode()->getOpcode() == ISD::BUILD_PAIR && "Call
>> lowered wrongly!");
>> Lo = Hi.getOperand(0); Hi = Hi.getOperand(1);
>> }
>>
>> @@ -790,7 +790,7 @@
>> == TargetLowering::Custom)
>> Res = TLI.LowerOperation(SDValue(N, OpNo), DAG);
>>
>> - if (Res.Val == 0) {
>> + if (Res.getNode() == 0) {
>> switch (N->getOpcode()) {
>> default:
>> #ifndef NDEBUG
>> @@ -816,10 +816,10 @@
>> }
>>
>> // If the result is null, the sub-method took care of registering
>> results etc.
>> - if (!Res.Val) return false;
>> + if (!Res.getNode()) return false;
>> // If the result is N, the sub-method updated N in place. Check
>> to see if any
>> // operands are new, and if so, mark them.
>> - if (Res.Val == N) {
>> + if (Res.getNode() == N) {
>> // Mark N as new and remark N and its operands. This allows us
>> to correctly
>> // revisit N if it needs another step of expansion and allows us
>> to visit
>> // any new operands to N.
>> @@ -869,7 +869,7 @@
>>
>> // If ExpandSetCCOperands returned a scalar, we need to compare
>> the result
>> // against zero to select between true and false values.
>> - if (NewRHS.Val == 0) {
>> + if (NewRHS.getNode() == 0) {
>> NewRHS = DAG.getConstant(0, NewLHS.getValueType());
>> CCCode = ISD::SETNE;
>> }
>> @@ -910,7 +910,7 @@
>>
>> // If ExpandSetCCOperands returned a scalar, we need to compare
>> the result
>> // against zero to select between true and false values.
>> - if (NewRHS.Val == 0) {
>> + if (NewRHS.getNode() == 0) {
>> NewRHS = DAG.getConstant(0, NewLHS.getValueType());
>> CCCode = ISD::SETNE;
>> }
>> @@ -927,7 +927,7 @@
>> FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode);
>>
>> // If ExpandSetCCOperands returned a scalar, use it.
>> - if (NewRHS.Val == 0) {
>> + if (NewRHS.getNode() == 0) {
>> assert(NewLHS.getValueType() == N->getValueType(0) &&
>> "Unexpected setcc expansion!");
>> return NewLHS;
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/
>> LegalizeIntegerTypes.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
>> (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Thu
>> Aug 28 16:40:38 2008
>> @@ -99,7 +99,7 @@
>> }
>>
>> // If Result is null, the sub-method took care of registering the
>> result.
>> - if (Result.Val)
>> + if (Result.getNode())
>> SetPromotedInteger(SDValue(N, ResNo), Result);
>> }
>>
>> @@ -167,7 +167,7 @@
>> // Otherwise, lower the bit-convert to a store/load from the
>> stack, then
>> // promote the load.
>> SDValue Op = CreateStackStoreLoad(InOp, N->getValueType(0));
>> - return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.Val));
>> + return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.getNode()));
>> }
>>
>> SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
>> @@ -494,7 +494,7 @@
>> == TargetLowering::Custom)
>> Res = TLI.LowerOperation(SDValue(N, OpNo), DAG);
>>
>> - if (Res.Val == 0) {
>> + if (Res.getNode() == 0) {
>> switch (N->getOpcode()) {
>> default:
>> #ifndef NDEBUG
>> @@ -529,9 +529,9 @@
>> }
>>
>> // If the result is null, the sub-method took care of registering
>> results etc.
>> - if (!Res.Val) return false;
>> + if (!Res.getNode()) return false;
>> // If the result is N, the sub-method updated N in place.
>> - if (Res.Val == N) {
>> + if (Res.getNode() == N) {
>> // Mark N as new and remark N and its operands. This allows us
>> to correctly
>> // revisit N if it needs another step of promotion and allows us
>> to visit
>> // any new operands to N.
>> @@ -885,7 +885,7 @@
>> }
>>
>> // If Lo/Hi is null, the sub-method took care of registering
>> results etc.
>> - if (Lo.Val)
>> + if (Lo.getNode())
>> SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
>> }
>>
>> @@ -1395,7 +1395,7 @@
>> if (HasUMUL_LOHI) {
>> // We can emit a umul_lohi.
>> Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT),
>> LL, RL);
>> - Hi = SDValue(Lo.Val, 1);
>> + Hi = SDValue(Lo.getNode(), 1);
>> return;
>> }
>> if (HasMULHU) {
>> @@ -1410,7 +1410,7 @@
>> if (HasSMUL_LOHI) {
>> // We can emit a smul_lohi.
>> Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT),
>> LL, RL);
>> - Hi = SDValue(Lo.Val, 1);
>> + Hi = SDValue(Lo.getNode(), 1);
>> return;
>> }
>> if (HasMULHS) {
>> @@ -1706,7 +1706,7 @@
>> == TargetLowering::Custom)
>> Res = TLI.LowerOperation(SDValue(N, OpNo), DAG);
>>
>> - if (Res.Val == 0) {
>> + if (Res.getNode() == 0) {
>> switch (N->getOpcode()) {
>> default:
>> #ifndef NDEBUG
>> @@ -1732,10 +1732,10 @@
>> }
>>
>> // If the result is null, the sub-method took care of registering
>> results etc.
>> - if (!Res.Val) return false;
>> + if (!Res.getNode()) return false;
>> // If the result is N, the sub-method updated N in place. Check
>> to see if any
>> // operands are new, and if so, mark them.
>> - if (Res.Val == N) {
>> + if (Res.getNode() == N) {
>> // Mark N as new and remark N and its operands. This allows us
>> to correctly
>> // revisit N if it needs another step of expansion and allows us
>> to visit
>> // any new operands to N.
>> @@ -1814,16 +1814,16 @@
>> SDValue Tmp1, Tmp2;
>> Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo,
>> RHSLo, LowCC,
>> false, DagCombineInfo);
>> - if (!Tmp1.Val)
>> + if (!Tmp1.getNode())
>> Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
>> LowCC);
>> Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi,
>> RHSHi,
>> CCCode, false, DagCombineInfo);
>> - if (!Tmp2.Val)
>> + if (!Tmp2.getNode())
>> Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi),
>> LHSHi, RHSHi,
>> DAG.getCondCode(CCCode));
>>
>> - ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
>> - ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
>> + ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
>> + ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
>> if ((Tmp1C && Tmp1C->isNullValue()) ||
>> (Tmp2C && Tmp2C->isNullValue() &&
>> (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
>> @@ -1841,7 +1841,7 @@
>>
>> NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi,
>> RHSHi,
>> ISD::SETEQ, false, DagCombineInfo);
>> - if (!NewLHS.Val)
>> + if (!NewLHS.getNode())
>> NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
>> ISD::SETEQ);
>> NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
>> @@ -1856,7 +1856,7 @@
>>
>> // If ExpandSetCCOperands returned a scalar, we need to compare
>> the result
>> // against zero to select between true and false values.
>> - if (NewRHS.Val == 0) {
>> + if (NewRHS.getNode() == 0) {
>> NewRHS = DAG.getConstant(0, NewLHS.getValueType());
>> CCCode = ISD::SETNE;
>> }
>> @@ -1874,7 +1874,7 @@
>>
>> // If ExpandSetCCOperands returned a scalar, we need to compare
>> the result
>> // against zero to select between true and false values.
>> - if (NewRHS.Val == 0) {
>> + if (NewRHS.getNode() == 0) {
>> NewRHS = DAG.getConstant(0, NewLHS.getValueType());
>> CCCode = ISD::SETNE;
>> }
>> @@ -1891,7 +1891,7 @@
>> IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
>>
>> // If ExpandSetCCOperands returned a scalar, use it.
>> - if (NewRHS.Val == 0) {
>> + if (NewRHS.getNode() == 0) {
>> assert(NewLHS.getValueType() == N->getValueType(0) &&
>> "Unexpected setcc expansion!");
>> return NewLHS;
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -92,7 +92,7 @@
>> bool NeedsRevisit = false;
>> unsigned i;
>> for (i = 0; i != NumOperands; ++i) {
>> - if (IgnoreNodeResults(N->getOperand(i).Val))
>> + if (IgnoreNodeResults(N->getOperand(i).getNode()))
>> continue;
>>
>> MVT OpVT = N->getOperand(i).getValueType();
>> @@ -194,7 +194,7 @@
>>
>> // Check that all operand types are legal.
>> for (unsigned i = 0, NumOps = I->getNumOperands(); i < NumOps; +
>> +i)
>> - if (!IgnoreNodeResults(I->getOperand(i).Val) &&
>> + if (!IgnoreNodeResults(I->getOperand(i).getNode()) &&
>> !isTypeLegal(I->getOperand(i).getValueType())) {
>> cerr << "Operand type " << i << " illegal!\n";
>> Failed = true;
>> @@ -221,7 +221,8 @@
>> /// AnalyzeNewNode - The specified node is the root of a subtree of
>> potentially
>> /// new nodes. Correct any processed operands (this may change the
>> node) and
>> /// calculate the NodeId.
>> -void DAGTypeLegalizer::AnalyzeNewNode(SDNode *&N) {
>> +void DAGTypeLegalizer::AnalyzeNewNode(SDValue &Val) {
>> + SDNode * const N(Val.getNode());
>> // If this was an existing node that is already done, we're done.
>> if (N->getNodeId() != NewNode)
>> return;
>> @@ -246,12 +247,12 @@
>> SDValue OrigOp = N->getOperand(i);
>> SDValue Op = OrigOp;
>>
>> - if (Op.Val->getNodeId() == Processed)
>> + if (Op.getNode()->getNodeId() == Processed)
>> RemapNode(Op);
>>
>> - if (Op.Val->getNodeId() == NewNode)
>> - AnalyzeNewNode(Op.Val);
>> - else if (Op.Val->getNodeId() == Processed)
>> + if (Op.getNode()->getNodeId() == NewNode)
>> + AnalyzeNewNode(Op);
>> + else if (Op.getNode()->getNodeId() == Processed)
>> ++NumProcessed;
>>
>> if (!NewOps.empty()) {
>> @@ -267,11 +268,14 @@
>>
>> // Some operands changed - update the node.
>> if (!NewOps.empty())
>> - N = DAG.UpdateNodeOperands(SDValue(N, 0), &NewOps[0],
>> NewOps.size()).Val;
>> -
>> - N->setNodeId(N->getNumOperands()-NumProcessed);
>> - if (N->getNodeId() == ReadyToProcess)
>> - Worklist.push_back(N);
>> + Val.setNode(DAG.UpdateNodeOperands(SDValue(N, 0),
>> + &NewOps[0],
>> + NewOps.size()).getNode());
>> +
>> + SDNode * const Nu(Val.getNode());
>> + Nu->setNodeId(Nu->getNumOperands()-NumProcessed);
>> + if (Nu->getNodeId() == ReadyToProcess)
>> + Worklist.push_back(Nu);
>> }
>>
>> namespace {
>> @@ -313,8 +317,8 @@
>> if (From == To) return;
>>
>> // If expansion produced new nodes, make sure they are properly
>> marked.
>> - ExpungeNode(From.Val);
>> - AnalyzeNewNode(To.Val); // Expunges To.
>> + ExpungeNode(From.getNode());
>> + AnalyzeNewNode(To); // Expunges To.
>>
>> // Anything that used the old node should now use the new one.
>> Note that this
>> // can potentially cause recursive merging.
>> @@ -333,7 +337,10 @@
>>
>> // If expansion produced new nodes, make sure they are properly
>> marked.
>> ExpungeNode(From);
>> - AnalyzeNewNode(To); // Expunges To.
>> +
>> + SDValue ToNode(To, 0);
>> + AnalyzeNewNode(ToNode); // Expunges To.
>> + To = ToNode.getNode();
>>
>> assert(From->getNumValues() == To->getNumValues() &&
>> "Node results don't match");
>> @@ -394,39 +401,39 @@
>>
>> for (DenseMap<SDValue, SDValue>::iterator I =
>> PromotedIntegers.begin(),
>> E = PromotedIntegers.end(); I != E; ++I) {
>> - assert(I->first.Val != N);
>> + assert(I->first.getNode() != N);
>> RemapNode(I->second);
>> }
>>
>> for (DenseMap<SDValue, SDValue>::iterator I =
>> SoftenedFloats.begin(),
>> E = SoftenedFloats.end(); I != E; ++I) {
>> - assert(I->first.Val != N);
>> + assert(I->first.getNode() != N);
>> RemapNode(I->second);
>> }
>>
>> for (DenseMap<SDValue, SDValue>::iterator I =
>> ScalarizedVectors.begin(),
>> E = ScalarizedVectors.end(); I != E; ++I) {
>> - assert(I->first.Val != N);
>> + assert(I->first.getNode() != N);
>> RemapNode(I->second);
>> }
>>
>> for (DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator
>> I = ExpandedIntegers.begin(), E = ExpandedIntegers.end(); I !
>> = E; ++I){
>> - assert(I->first.Val != N);
>> + assert(I->first.getNode() != N);
>> RemapNode(I->second.first);
>> RemapNode(I->second.second);
>> }
>>
>> for (DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator
>> I = ExpandedFloats.begin(), E = ExpandedFloats.end(); I != E;
>> ++I) {
>> - assert(I->first.Val != N);
>> + assert(I->first.getNode() != N);
>> RemapNode(I->second.first);
>> RemapNode(I->second.second);
>> }
>>
>> for (DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator
>> I = SplitVectors.begin(), E = SplitVectors.end(); I != E; +
>> +I) {
>> - assert(I->first.Val != N);
>> + assert(I->first.getNode() != N);
>> RemapNode(I->second.first);
>> RemapNode(I->second.second);
>> }
>> @@ -440,26 +447,26 @@
>> }
>>
>> void DAGTypeLegalizer::SetPromotedInteger(SDValue Op, SDValue
>> Result) {
>> - AnalyzeNewNode(Result.Val);
>> + AnalyzeNewNode(Result);
>>
>> SDValue &OpEntry = PromotedIntegers[Op];
>> - assert(OpEntry.Val == 0 && "Node is already promoted!");
>> + assert(OpEntry.getNode() == 0 && "Node is already promoted!");
>> OpEntry = Result;
>> }
>>
>> void DAGTypeLegalizer::SetSoftenedFloat(SDValue Op, SDValue Result) {
>> - AnalyzeNewNode(Result.Val);
>> + AnalyzeNewNode(Result);
>>
>> SDValue &OpEntry = SoftenedFloats[Op];
>> - assert(OpEntry.Val == 0 && "Node is already converted to
>> integer!");
>> + assert(OpEntry.getNode() == 0 && "Node is already converted to
>> integer!");
>> OpEntry = Result;
>> }
>>
>> void DAGTypeLegalizer::SetScalarizedVector(SDValue Op, SDValue
>> Result) {
>> - AnalyzeNewNode(Result.Val);
>> + AnalyzeNewNode(Result);
>>
>> SDValue &OpEntry = ScalarizedVectors[Op];
>> - assert(OpEntry.Val == 0 && "Node is already scalarized!");
>> + assert(OpEntry.getNode() == 0 && "Node is already scalarized!");
>> OpEntry = Result;
>> }
>>
>> @@ -468,7 +475,7 @@
>> std::pair<SDValue, SDValue> &Entry = ExpandedIntegers[Op];
>> RemapNode(Entry.first);
>> RemapNode(Entry.second);
>> - assert(Entry.first.Val && "Operand isn't expanded");
>> + assert(Entry.first.getNode() && "Operand isn't expanded");
>> Lo = Entry.first;
>> Hi = Entry.second;
>> }
>> @@ -476,12 +483,12 @@
>> void DAGTypeLegalizer::SetExpandedInteger(SDValue Op, SDValue Lo,
>> SDValue Hi) {
>> // Lo/Hi may have been newly allocated, if so, add nodeid's as
>> relevant.
>> - AnalyzeNewNode(Lo.Val);
>> - AnalyzeNewNode(Hi.Val);
>> + AnalyzeNewNode(Lo);
>> + AnalyzeNewNode(Hi);
>>
>> // Remember that this is the result of the node.
>> std::pair<SDValue, SDValue> &Entry = ExpandedIntegers[Op];
>> - assert(Entry.first.Val == 0 && "Node already expanded");
>> + assert(Entry.first.getNode() == 0 && "Node already expanded");
>> Entry.first = Lo;
>> Entry.second = Hi;
>> }
>> @@ -491,7 +498,7 @@
>> std::pair<SDValue, SDValue> &Entry = ExpandedFloats[Op];
>> RemapNode(Entry.first);
>> RemapNode(Entry.second);
>> - assert(Entry.first.Val && "Operand isn't expanded");
>> + assert(Entry.first.getNode() && "Operand isn't expanded");
>> Lo = Entry.first;
>> Hi = Entry.second;
>> }
>> @@ -499,12 +506,12 @@
>> void DAGTypeLegalizer::SetExpandedFloat(SDValue Op, SDValue Lo,
>> SDValue Hi) {
>> // Lo/Hi may have been newly allocated, if so, add nodeid's as
>> relevant.
>> - AnalyzeNewNode(Lo.Val);
>> - AnalyzeNewNode(Hi.Val);
>> + AnalyzeNewNode(Lo);
>> + AnalyzeNewNode(Hi);
>>
>> // Remember that this is the result of the node.
>> std::pair<SDValue, SDValue> &Entry = ExpandedFloats[Op];
>> - assert(Entry.first.Val == 0 && "Node already expanded");
>> + assert(Entry.first.getNode() == 0 && "Node already expanded");
>> Entry.first = Lo;
>> Entry.second = Hi;
>> }
>> @@ -514,7 +521,7 @@
>> std::pair<SDValue, SDValue> &Entry = SplitVectors[Op];
>> RemapNode(Entry.first);
>> RemapNode(Entry.second);
>> - assert(Entry.first.Val && "Operand isn't split");
>> + assert(Entry.first.getNode() && "Operand isn't split");
>> Lo = Entry.first;
>> Hi = Entry.second;
>> }
>> @@ -522,12 +529,12 @@
>> void DAGTypeLegalizer::SetSplitVector(SDValue Op, SDValue Lo,
>> SDValue Hi) {
>> // Lo/Hi may have been newly allocated, if so, add nodeid's as
>> relevant.
>> - AnalyzeNewNode(Lo.Val);
>> - AnalyzeNewNode(Hi.Val);
>> + AnalyzeNewNode(Lo);
>> + AnalyzeNewNode(Hi);
>>
>> // Remember that this is the result of the node.
>> std::pair<SDValue, SDValue> &Entry = SplitVectors[Op];
>> - assert(Entry.first.Val == 0 && "Node already split");
>> + assert(Entry.first.getNode() == 0 && "Node already split");
>> Entry.first = Lo;
>> Entry.second = Hi;
>> }
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Thu Aug 28
>> 16:40:38 2008
>> @@ -157,7 +157,8 @@
>> /// for the specified node, adding it to the worklist if ready.
>> void ReanalyzeNode(SDNode *N) {
>> N->setNodeId(NewNode);
>> - AnalyzeNewNode(N);
>> + SDValue V(N, 0);
>> + AnalyzeNewNode(V); // FIXME: ignore the change?
>> }
>>
>> void NoteDeletion(SDNode *Old, SDNode *New) {
>> @@ -168,7 +169,7 @@
>> }
>>
>> private:
>> - void AnalyzeNewNode(SDNode *&N);
>> + void AnalyzeNewNode(SDValue &Val);
>>
>> void ReplaceValueWith(SDValue From, SDValue To);
>> void ReplaceNodeWith(SDNode *From, SDNode *To);
>> @@ -197,7 +198,7 @@
>> SDValue GetPromotedInteger(SDValue Op) {
>> SDValue &PromotedOp = PromotedIntegers[Op];
>> RemapNode(PromotedOp);
>> - assert(PromotedOp.Val && "Operand wasn't promoted?");
>> + assert(PromotedOp.getNode() && "Operand wasn't promoted?");
>> return PromotedOp;
>> }
>> void SetPromotedInteger(SDValue Op, SDValue Result);
>> @@ -324,7 +325,7 @@
>> SDValue GetSoftenedFloat(SDValue Op) {
>> SDValue &SoftenedOp = SoftenedFloats[Op];
>> RemapNode(SoftenedOp);
>> - assert(SoftenedOp.Val && "Operand wasn't converted to
>> integer?");
>> + assert(SoftenedOp.getNode() && "Operand wasn't converted to
>> integer?");
>> return SoftenedOp;
>> }
>> void SetSoftenedFloat(SDValue Op, SDValue Result);
>> @@ -403,7 +404,7 @@
>> SDValue GetScalarizedVector(SDValue Op) {
>> SDValue &ScalarizedOp = ScalarizedVectors[Op];
>> RemapNode(ScalarizedOp);
>> - assert(ScalarizedOp.Val && "Operand wasn't scalarized?");
>> + assert(ScalarizedOp.getNode() && "Operand wasn't scalarized?");
>> return ScalarizedOp;
>> }
>> void SetScalarizedVector(SDValue Op, SDValue Result);
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/
>> LegalizeTypesGeneric.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
>> (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp Thu
>> Aug 28 16:40:38 2008
>> @@ -75,7 +75,7 @@
>>
>> // Lower the bit-convert to a store/load from the stack, then
>> expand the load.
>> SDValue Op = CreateStackStoreLoad(InOp, N->getValueType(0));
>> - ExpandRes_NormalLoad(Op.Val, Lo, Hi);
>> + ExpandRes_NormalLoad(Op.getNode(), Lo, Hi);
>> }
>>
>> void DAGTypeLegalizer::ExpandRes_BUILD_PAIR(SDNode *N, SDValue &Lo,
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
>> (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Thu
>> Aug 28 16:40:38 2008
>> @@ -88,7 +88,7 @@
>> }
>>
>> // If R is null, the sub-method took care of registering the result.
>> - if (R.Val)
>> + if (R.getNode())
>> SetScalarizedVector(SDValue(N, ResNo), R);
>> }
>>
>> @@ -184,7 +184,7 @@
>> cerr << "\n");
>> SDValue Res = SDValue();
>>
>> - if (Res.Val == 0) {
>> + if (Res.getNode() == 0) {
>> switch (N->getOpcode()) {
>> default:
>> #ifndef NDEBUG
>> @@ -206,11 +206,11 @@
>> }
>>
>> // If the result is null, the sub-method took care of registering
>> results etc.
>> - if (!Res.Val) return false;
>> + if (!Res.getNode()) return false;
>>
>> // If the result is N, the sub-method updated N in place. Check
>> to see if any
>> // operands are new, and if so, mark them.
>> - if (Res.Val == N) {
>> + if (Res.getNode() == N) {
>> // Mark N as new and remark N and its operands. This allows us
>> to correctly
>> // revisit N if it needs another step of promotion and allows us
>> to visit
>> // any new operands to N.
>> @@ -332,7 +332,7 @@
>> }
>>
>> // If Lo/Hi is null, the sub-method took care of registering
>> results etc.
>> - if (Lo.Val)
>> + if (Lo.getNode())
>> SetSplitVector(SDValue(N, ResNo), Lo, Hi);
>> }
>>
>> @@ -475,7 +475,7 @@
>> SDValue Load = DAG.getLoad(VecVT, Store, StackPtr, NULL, 0);
>>
>> // Split it.
>> - SplitVecRes_LOAD(cast<LoadSDNode>(Load.Val), Lo, Hi);
>> + SplitVecRes_LOAD(cast<LoadSDNode>(Load.getNode()), Lo, Hi);
>> }
>>
>> void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
>> @@ -595,7 +595,7 @@
>> DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n");
>> SDValue Res = SDValue();
>>
>> - if (Res.Val == 0) {
>> + if (Res.getNode() == 0) {
>> switch (N->getOpcode()) {
>> default:
>> #ifndef NDEBUG
>> @@ -615,11 +615,11 @@
>> }
>>
>> // If the result is null, the sub-method took care of registering
>> results etc.
>> - if (!Res.Val) return false;
>> + if (!Res.getNode()) return false;
>>
>> // If the result is N, the sub-method updated N in place. Check
>> to see if any
>> // operands are new, and if so, mark them.
>> - if (Res.Val == N) {
>> + if (Res.getNode() == N) {
>> // Mark N as new and remark N and its operands. This allows us
>> to correctly
>> // revisit N if it needs another step of promotion and allows us
>> to visit
>> // any new operands to N.
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -122,7 +122,7 @@
>> if (N->getNumOperands() &&
>> N->getOperand(N->getNumOperands()-1).getValueType() ==
>> MVT::Flag) {
>> do {
>> - N = N->getOperand(N->getNumOperands()-1).Val;
>> + N = N->getOperand(N->getNumOperands()-1).getNode();
>> NodeSUnit->FlaggedNodes.push_back(N);
>> assert(N->getNodeId() == -1 && "Node already inserted!");
>> N->setNodeId(NodeSUnit->NodeNum);
>> @@ -192,7 +192,7 @@
>> SU->hasPhysRegDefs = true;
>>
>> for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
>> - SDNode *OpN = N->getOperand(i).Val;
>> + SDNode *OpN = N->getOperand(i).getNode();
>> if (isPassiveNode(OpN)) continue; // Not scheduled.
>> SUnit *OpSU = &SUnits[OpN->getNodeId()];
>> assert(OpSU && "Node has no SUnit!");
>> @@ -373,7 +373,7 @@
>> /// actual operands that will go into the resulting MachineInstr.
>> unsigned ScheduleDAG::CountOperands(SDNode *Node) {
>> unsigned N = ComputeMemOperandsEnd(Node);
>> - while (N && isa<MemOperandSDNode>(Node->getOperand(N - 1).Val))
>> + while (N && isa<MemOperandSDNode>(Node->getOperand(N -
>> 1).getNode()))
>> --N; // Ignore MEMOPERAND nodes
>> return N;
>> }
>> @@ -429,7 +429,7 @@
>> SDNode *User = *UI;
>> bool Match = true;
>> if (User->getOpcode() == ISD::CopyToReg &&
>> - User->getOperand(2).Val == Node &&
>> + User->getOperand(2).getNode() == Node &&
>> User->getOperand(2).getResNo() == ResNo) {
>> unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))-
>>> getReg();
>> if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
>> @@ -440,7 +440,7 @@
>> } else {
>> for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
>> SDValue Op = User->getOperand(i);
>> - if (Op.Val != Node || Op.getResNo() != ResNo)
>> + if (Op.getNode() != Node || Op.getResNo() != ResNo)
>> continue;
>> MVT VT = Node->getValueType(Op.getResNo());
>> if (VT != MVT::Other && VT != MVT::Flag)
>> @@ -489,7 +489,7 @@
>>
>> SDNode *User = *Node->use_begin();
>> if (User->getOpcode() == ISD::CopyToReg &&
>> - User->getOperand(2).Val == Node &&
>> + User->getOperand(2).getNode() == Node &&
>> User->getOperand(2).getResNo() == ResNo) {
>> unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))-
>>> getReg();
>> if (TargetRegisterInfo::isVirtualRegister(Reg))
>> @@ -513,7 +513,7 @@
>> UI != E; ++UI) {
>> SDNode *User = *UI;
>> if (User->getOpcode() == ISD::CopyToReg &&
>> - User->getOperand(2).Val == Node &&
>> + User->getOperand(2).getNode() == Node &&
>> User->getOperand(2).getResNo() == i) {
>> unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))-
>>> getReg();
>> if (TargetRegisterInfo::isVirtualRegister(Reg)) {
>> @@ -547,7 +547,7 @@
>> if (Op.isMachineOpcode() &&
>> Op.getMachineOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
>> // Add an IMPLICIT_DEF instruction before every use.
>> - unsigned VReg = getDstOfOnlyCopyToRegUse(Op.Val, Op.getResNo());
>> + unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(),
>> Op.getResNo());
>> // IMPLICIT_DEF can produce any type of result so its
>> TargetInstrDesc
>> // does not include operand register class info.
>> if (!VReg) {
>> @@ -600,7 +600,7 @@
>> if (RC && VRC != RC) {
>> cerr << "Register class of operand and regclass of use don't
>> agree!\n";
>> cerr << "Operand = " << IIOpNum << "\n";
>> - cerr << "Op->Val = "; Op.Val->dump(&DAG); cerr << "\n";
>> + cerr << "Op->Val = "; Op.getNode()->dump(&DAG); cerr <<
>> "\n";
>> cerr << "MI = "; MI->print(cerr);
>> cerr << "VReg = " << VReg << "\n";
>> cerr << "VReg RegClass size = " << VRC->getSize()
>> @@ -712,7 +712,7 @@
>> UI != E; ++UI) {
>> SDNode *User = *UI;
>> if (User->getOpcode() == ISD::CopyToReg &&
>> - User->getOperand(2).Val == Node) {
>> + User->getOperand(2).getNode() == Node) {
>> unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))-
>>> getReg();
>> if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
>> VRBase = DestReg;
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>> (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Thu
>> Aug 28 16:40:38 2008
>> @@ -224,7 +224,7 @@
>> if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) == -1)
>> continue;
>>
>> - SDNode *OpN = SU->Node->getOperand(j).Val;
>> + SDNode *OpN = SU->Node->getOperand(j).getNode();
>> SUnit *OpSU = isPassiveNode(OpN) ? NULL : &SUnits[OpN-
>>> getNodeId()];
>> if (OpSU && OperandSeen.count(OpSU) == 1) {
>> // Ok, so SU is not the last use of OpSU, but SU is two-
>> address so
>> @@ -233,7 +233,7 @@
>> bool DoCommute = true;
>> for (unsigned k = 0; k < NumOps; ++k) {
>> if (k != j) {
>> - OpN = SU->Node->getOperand(k).Val;
>> + OpN = SU->Node->getOperand(k).getNode();
>> OpSU = isPassiveNode(OpN) ? NULL : &SUnits[OpN-
>>> getNodeId()];
>> if (OpSU && OperandSeen.count(OpSU) == 1) {
>> DoCommute = false;
>> @@ -641,7 +641,7 @@
>> }
>> for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
>> const SDValue &Op = N->getOperand(i);
>> - MVT VT = Op.Val->getValueType(Op.getResNo());
>> + MVT VT = Op.getNode()->getValueType(Op.getResNo());
>> if (VT == MVT::Flag)
>> return NULL;
>> }
>> @@ -930,7 +930,7 @@
>> unsigned CurCycle = 0;
>> // Add root to Available queue.
>> if (!SUnits.empty()) {
>> - SUnit *RootSU = &SUnits[DAG.getRoot().Val->getNodeId()];
>> + SUnit *RootSU = &SUnits[DAG.getRoot().getNode()->getNodeId()];
>> assert(RootSU->Succs.empty() && "Graph root shouldn't have
>> successors!");
>> RootSU->isAvailable = true;
>> AvailableQueue->push(RootSU);
>> @@ -1668,7 +1668,7 @@
>> unsigned NumOps = TID.getNumOperands() - NumRes;
>> for (unsigned i = 0; i != NumOps; ++i) {
>> if (TID.getOperandConstraint(i+NumRes, TOI::TIED_TO) != -1) {
>> - SDNode *DU = SU->Node->getOperand(i).Val;
>> + SDNode *DU = SU->Node->getOperand(i).getNode();
>> if (DU->getNodeId() != -1 &&
>> Op->OrigNode == &(*SUnits)[DU->getNodeId()])
>> return true;
>> @@ -1742,7 +1742,7 @@
>> unsigned NumOps = TID.getNumOperands() - NumRes;
>> for (unsigned j = 0; j != NumOps; ++j) {
>> if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) != -1) {
>> - SDNode *DU = SU->Node->getOperand(j).Val;
>> + SDNode *DU = SU->Node->getOperand(j).getNode();
>> if (DU->getNodeId() == -1)
>> continue;
>> const SUnit *DUSU = &(*SUnits)[DU->getNodeId()];
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -96,7 +96,7 @@
>> bool ISD::isBuildVectorAllOnes(const SDNode *N) {
>> // Look through a bit convert.
>> if (N->getOpcode() == ISD::BIT_CONVERT)
>> - N = N->getOperand(0).Val;
>> + N = N->getOperand(0).getNode();
>>
>> if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
>>
>> @@ -137,7 +137,7 @@
>> bool ISD::isBuildVectorAllZeros(const SDNode *N) {
>> // Look through a bit convert.
>> if (N->getOpcode() == ISD::BIT_CONVERT)
>> - N = N->getOperand(0).Val;
>> + N = N->getOperand(0).getNode();
>>
>> if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
>>
>> @@ -326,7 +326,7 @@
>> static void AddNodeIDOperands(FoldingSetNodeID &ID,
>> const SDValue *Ops, unsigned NumOps) {
>> for (; NumOps; --NumOps, ++Ops) {
>> - ID.AddPointer(Ops->Val);
>> + ID.AddPointer(Ops->getNode());
>> ID.AddInteger(Ops->getResNo());
>> }
>> }
>> @@ -1230,9 +1230,9 @@
>> break;
>> }
>>
>> - if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val)) {
>> + if (ConstantSDNode *N2C =
>> dyn_cast<ConstantSDNode>(N2.getNode())) {
>> const APInt &C2 = N2C->getAPIntValue();
>> - if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
>> + if (ConstantSDNode *N1C =
>> dyn_cast<ConstantSDNode>(N1.getNode())) {
>> const APInt &C1 = N1C->getAPIntValue();
>>
>> switch (Cond) {
>> @@ -1250,8 +1250,8 @@
>> }
>> }
>> }
>> - if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
>> - if (ConstantFPSDNode *N2C =
>> dyn_cast<ConstantFPSDNode>(N2.Val)) {
>> + if (ConstantFPSDNode *N1C =
>> dyn_cast<ConstantFPSDNode>(N1.getNode())) {
>> + if (ConstantFPSDNode *N2C =
>> dyn_cast<ConstantFPSDNode>(N2.getNode())) {
>> // No compile time operations on this type yet.
>> if (N1C->getValueType(0) == MVT::ppcf128)
>> return SDValue();
>> @@ -1572,7 +1572,7 @@
>> return;
>> }
>> case ISD::LOAD: {
>> - if (ISD::isZEXTLoad(Op.Val)) {
>> + if (ISD::isZEXTLoad(Op.getNode())) {
>> LoadSDNode *LD = cast<LoadSDNode>(Op);
>> MVT VT = LD->getMemoryVT();
>> unsigned MemBits = VT.getSizeInBits();
>> @@ -2024,7 +2024,7 @@
>> if (V.getOpcode() == ISD::BUILD_VECTOR)
>> return V.getOperand(Index);
>> if (V.getOpcode() == ISD::VECTOR_SHUFFLE)
>> - return getShuffleScalarElt(V.Val, Index);
>> + return getShuffleScalarElt(V.getNode(), Index);
>> return SDValue();
>> }
>>
>> @@ -2050,7 +2050,7 @@
>>
>> SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, SDValue
>> Operand) {
>> // Constant fold unary operations with an integer constant operand.
>> - if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.Val)) {
>> + if (ConstantSDNode *C =
>> dyn_cast<ConstantSDNode>(Operand.getNode())) {
>> const APInt &Val = C->getAPIntValue();
>> unsigned BitWidth = VT.getSizeInBits();
>> switch (Opcode) {
>> @@ -2091,7 +2091,7 @@
>> }
>>
>> // Constant fold unary operations with a floating point constant
>> operand.
>> - if (ConstantFPSDNode *C =
>> dyn_cast<ConstantFPSDNode>(Operand.Val)) {
>> + if (ConstantFPSDNode *C =
>> dyn_cast<ConstantFPSDNode>(Operand.getNode())) {
>> APFloat V = C->getValueAPF(); // make copy
>> if (VT != MVT::ppcf128 && Operand.getValueType() !=
>> MVT::ppcf128) {
>> switch (Opcode) {
>> @@ -2130,7 +2130,7 @@
>> }
>> }
>>
>> - unsigned OpOpcode = Operand.Val->getOpcode();
>> + unsigned OpOpcode = Operand.getNode()->getOpcode();
>> switch (Opcode) {
>> case ISD::TokenFactor:
>> case ISD::CONCAT_VECTORS:
>> @@ -2150,7 +2150,7 @@
>> assert(Operand.getValueType().bitsLT(VT)
>> && "Invalid sext node, dst < src!");
>> if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
>> - return getNode(OpOpcode, VT, Operand.Val->getOperand(0));
>> + return getNode(OpOpcode, VT, Operand.getNode()-
>> >getOperand(0));
>> break;
>> case ISD::ZERO_EXTEND:
>> assert(VT.isInteger() && Operand.getValueType().isInteger() &&
>> @@ -2159,7 +2159,7 @@
>> assert(Operand.getValueType().bitsLT(VT)
>> && "Invalid zext node, dst < src!");
>> if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x)
>> - return getNode(ISD::ZERO_EXTEND, VT, Operand.Val-
>>> getOperand(0));
>> + return getNode(ISD::ZERO_EXTEND, VT, Operand.getNode()-
>>> getOperand(0));
>> break;
>> case ISD::ANY_EXTEND:
>> assert(VT.isInteger() && Operand.getValueType().isInteger() &&
>> @@ -2169,7 +2169,7 @@
>> && "Invalid anyext node, dst < src!");
>> if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND)
>> // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x)
>> - return getNode(OpOpcode, VT, Operand.Val->getOperand(0));
>> + return getNode(OpOpcode, VT, Operand.getNode()-
>> >getOperand(0));
>> break;
>> case ISD::TRUNCATE:
>> assert(VT.isInteger() && Operand.getValueType().isInteger() &&
>> @@ -2178,16 +2178,16 @@
>> assert(Operand.getValueType().bitsGT(VT)
>> && "Invalid truncate node, src < dst!");
>> if (OpOpcode == ISD::TRUNCATE)
>> - return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0));
>> + return getNode(ISD::TRUNCATE, VT, Operand.getNode()-
>>> getOperand(0));
>> else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode ==
>> ISD::SIGN_EXTEND ||
>> OpOpcode == ISD::ANY_EXTEND) {
>> // If the source is smaller than the dest, we still need an
>> extend.
>> - if (Operand.Val->getOperand(0).getValueType().bitsLT(VT))
>> - return getNode(OpOpcode, VT, Operand.Val->getOperand(0));
>> - else if (Operand.Val->getOperand(0).getValueType().bitsGT(VT))
>> - return getNode(ISD::TRUNCATE, VT, Operand.Val-
>>> getOperand(0));
>> + if (Operand.getNode()-
>> >getOperand(0).getValueType().bitsLT(VT))
>> + return getNode(OpOpcode, VT, Operand.getNode()-
>>> getOperand(0));
>> + else if (Operand.getNode()-
>>> getOperand(0).getValueType().bitsGT(VT))
>> + return getNode(ISD::TRUNCATE, VT, Operand.getNode()-
>>> getOperand(0));
>> else
>> - return Operand.Val->getOperand(0);
>> + return Operand.getNode()->getOperand(0);
>> }
>> break;
>> case ISD::BIT_CONVERT:
>> @@ -2215,14 +2215,14 @@
>> break;
>> case ISD::FNEG:
>> if (OpOpcode == ISD::FSUB) // -(X-Y) -> (Y-X)
>> - return getNode(ISD::FSUB, VT, Operand.Val->getOperand(1),
>> - Operand.Val->getOperand(0));
>> + return getNode(ISD::FSUB, VT, Operand.getNode()-
>> >getOperand(1),
>> + Operand.getNode()->getOperand(0));
>> if (OpOpcode == ISD::FNEG) // --X -> X
>> - return Operand.Val->getOperand(0);
>> + return Operand.getNode()->getOperand(0);
>> break;
>> case ISD::FABS:
>> if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X)
>> - return getNode(ISD::FABS, VT, Operand.Val->getOperand(0));
>> + return getNode(ISD::FABS, VT, Operand.getNode()-
>>> getOperand(0));
>> break;
>> }
>>
>> @@ -2252,8 +2252,8 @@
>>
>> SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
>> SDValue N1, SDValue N2) {
>> - ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
>> - ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
>> + ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
>> + ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
>> switch (Opcode) {
>> default: break;
>> case ISD::TokenFactor:
>> @@ -2268,8 +2268,8 @@
>> // one big BUILD_VECTOR.
>> if (N1.getOpcode() == ISD::BUILD_VECTOR &&
>> N2.getOpcode() == ISD::BUILD_VECTOR) {
>> - SmallVector<SDValue, 16> Elts(N1.Val->op_begin(), N1.Val-
>>> op_end());
>> - Elts.insert(Elts.end(), N2.Val->op_begin(), N2.Val->op_end());
>> + SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(),
>> N1.getNode()->op_end());
>> + Elts.insert(Elts.end(), N2.getNode()->op_begin(),
>> N2.getNode()->op_end());
>> return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size());
>> }
>> break;
>> @@ -2471,8 +2471,8 @@
>> }
>>
>> // Constant fold FP operations.
>> - ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.Val);
>> - ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.Val);
>> + ConstantFPSDNode *N1CFP =
>> dyn_cast<ConstantFPSDNode>(N1.getNode());
>> + ConstantFPSDNode *N2CFP =
>> dyn_cast<ConstantFPSDNode>(N2.getNode());
>> if (N1CFP) {
>> if (!N2CFP && isCommutativeBinOp(Opcode)) {
>> // Cannonicalize constant to RHS if commutative
>> @@ -2615,8 +2615,8 @@
>> SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
>> SDValue N1, SDValue N2, SDValue N3) {
>> // Perform various simplifications.
>> - ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
>> - ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
>> + ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
>> + ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
>> switch (Opcode) {
>> case ISD::CONCAT_VECTORS:
>> // A CONCAT_VECTOR with all operands BUILD_VECTOR can be
>> simplified to
>> @@ -2624,16 +2624,16 @@
>> if (N1.getOpcode() == ISD::BUILD_VECTOR &&
>> N2.getOpcode() == ISD::BUILD_VECTOR &&
>> N3.getOpcode() == ISD::BUILD_VECTOR) {
>> - SmallVector<SDValue, 16> Elts(N1.Val->op_begin(), N1.Val-
>>> op_end());
>> - Elts.insert(Elts.end(), N2.Val->op_begin(), N2.Val->op_end());
>> - Elts.insert(Elts.end(), N3.Val->op_begin(), N3.Val->op_end());
>> + SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(),
>> N1.getNode()->op_end());
>> + Elts.insert(Elts.end(), N2.getNode()->op_begin(),
>> N2.getNode()->op_end());
>> + Elts.insert(Elts.end(), N3.getNode()->op_begin(),
>> N3.getNode()->op_end());
>> return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size());
>> }
>> break;
>> case ISD::SETCC: {
>> // Use FoldSetCC to simplify SETCC's.
>> SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)-
>>> get());
>> - if (Simp.Val) return Simp;
>> + if (Simp.getNode()) return Simp;
>> break;
>> }
>> case ISD::SELECT:
>> @@ -3049,7 +3049,7 @@
>> SDValue Result =
>> getMemcpyLoadsAndStores(*this, Chain, Dst, Src, ConstantSize-
>>> getValue(),
>> Align, false, DstSV, DstSVOff, SrcSV,
>> SrcSVOff);
>> - if (Result.Val)
>> + if (Result.getNode())
>> return Result;
>> }
>>
>> @@ -3059,7 +3059,7 @@
>> TLI.EmitTargetCodeForMemcpy(*this, Chain, Dst, Src, Size, Align,
>> AlwaysInline,
>> DstSV, DstSVOff, SrcSV, SrcSVOff);
>> - if (Result.Val)
>> + if (Result.getNode())
>> return Result;
>>
>> // If we really need inline code and the target declined to
>> provide it,
>> @@ -3103,7 +3103,7 @@
>> SDValue Result =
>> getMemmoveLoadsAndStores(*this, Chain, Dst, Src, ConstantSize-
>>> getValue(),
>> Align, false, DstSV, DstSVOff, SrcSV,
>> SrcSVOff);
>> - if (Result.Val)
>> + if (Result.getNode())
>> return Result;
>> }
>>
>> @@ -3112,7 +3112,7 @@
>> SDValue Result =
>> TLI.EmitTargetCodeForMemmove(*this, Chain, Dst, Src, Size, Align,
>> DstSV, DstSVOff, SrcSV, SrcSVOff);
>> - if (Result.Val)
>> + if (Result.getNode())
>> return Result;
>>
>> // Emit a library call.
>> @@ -3146,7 +3146,7 @@
>> SDValue Result =
>> getMemsetStores(*this, Chain, Dst, Src, ConstantSize-
>>> getValue(), Align,
>> DstSV, DstSVOff);
>> - if (Result.Val)
>> + if (Result.getNode())
>> return Result;
>> }
>>
>> @@ -3155,7 +3155,7 @@
>> SDValue Result =
>> TLI.EmitTargetCodeForMemset(*this, Chain, Dst, Src, Size, Align,
>> DstSV, DstSVOff);
>> - if (Result.Val)
>> + if (Result.getNode())
>> return Result;
>>
>> // Emit a library call.
>> @@ -3737,7 +3737,7 @@
>> /// input node is returned. As a degenerate case, if you specify
>> the same
>> /// input operands as the node already has, the input node is
>> returned.
>> SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) {
>> - SDNode *N = InN.Val;
>> + SDNode *N = InN.getNode();
>> assert(N->getNumOperands() == 1 && "Update with wrong number of
>> operands");
>>
>> // Check to see if there is no change.
>> @@ -3756,7 +3756,7 @@
>> N->OperandList[0].getVal()->removeUser(0, N);
>> N->OperandList[0] = Op;
>> N->OperandList[0].setUser(N);
>> - Op.Val->addUser(0, N);
>> + Op.getNode()->addUser(0, N);
>>
>> // If this gets put into a CSE map, add it.
>> if (InsertPos) CSEMap.InsertNode(N, InsertPos);
>> @@ -3765,7 +3765,7 @@
>>
>> SDValue SelectionDAG::
>> UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) {
>> - SDNode *N = InN.Val;
>> + SDNode *N = InN.getNode();
>> assert(N->getNumOperands() == 2 && "Update with wrong number of
>> operands");
>>
>> // Check to see if there is no change.
>> @@ -3786,13 +3786,13 @@
>> N->OperandList[0].getVal()->removeUser(0, N);
>> N->OperandList[0] = Op1;
>> N->OperandList[0].setUser(N);
>> - Op1.Val->addUser(0, N);
>> + Op1.getNode()->addUser(0, N);
>> }
>> if (N->OperandList[1] != Op2) {
>> N->OperandList[1].getVal()->removeUser(1, N);
>> N->OperandList[1] = Op2;
>> N->OperandList[1].setUser(N);
>> - Op2.Val->addUser(1, N);
>> + Op2.getNode()->addUser(1, N);
>> }
>>
>> // If this gets put into a CSE map, add it.
>> @@ -3822,7 +3822,7 @@
>>
>> SDValue SelectionDAG::
>> UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned
>> NumOps) {
>> - SDNode *N = InN.Val;
>> + SDNode *N = InN.getNode();
>> assert(N->getNumOperands() == NumOps &&
>> "Update with wrong number of operands");
>>
>> @@ -3853,7 +3853,7 @@
>> N->OperandList[i].getVal()->removeUser(i, N);
>> N->OperandList[i] = Ops[i];
>> N->OperandList[i].setUser(N);
>> - Ops[i].Val->addUser(i, N);
>> + Ops[i].getNode()->addUser(i, N);
>> }
>> }
>>
>> @@ -4134,70 +4134,70 @@
>> /// node of the specified opcode and operands, it returns that node
>> instead of
>> /// the current one.
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) {
>> - return getNode(~Opcode, VT).Val;
>> + return getNode(~Opcode, VT).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDValue
>> Op1) {
>> - return getNode(~Opcode, VT, Op1).Val;
>> + return getNode(~Opcode, VT, Op1).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
>> SDValue Op1, SDValue Op2) {
>> - return getNode(~Opcode, VT, Op1, Op2).Val;
>> + return getNode(~Opcode, VT, Op1, Op2).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
>> SDValue Op1, SDValue Op2,
>> SDValue Op3) {
>> - return getNode(~Opcode, VT, Op1, Op2, Op3).Val;
>> + return getNode(~Opcode, VT, Op1, Op2, Op3).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
>> const SDValue *Ops, unsigned
>> NumOps) {
>> - return getNode(~Opcode, VT, Ops, NumOps).Val;
>> + return getNode(~Opcode, VT, Ops, NumOps).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT
>> VT2) {
>> const MVT *VTs = getNodeValueTypes(VT1, VT2);
>> SDValue Op;
>> - return getNode(~Opcode, VTs, 2, &Op, 0).Val;
>> + return getNode(~Opcode, VTs, 2, &Op, 0).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
>> MVT VT2, SDValue Op1) {
>> const MVT *VTs = getNodeValueTypes(VT1, VT2);
>> - return getNode(~Opcode, VTs, 2, &Op1, 1).Val;
>> + return getNode(~Opcode, VTs, 2, &Op1, 1).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
>> MVT VT2, SDValue Op1,
>> SDValue Op2) {
>> const MVT *VTs = getNodeValueTypes(VT1, VT2);
>> SDValue Ops[] = { Op1, Op2 };
>> - return getNode(~Opcode, VTs, 2, Ops, 2).Val;
>> + return getNode(~Opcode, VTs, 2, Ops, 2).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
>> MVT VT2, SDValue Op1,
>> SDValue Op2, SDValue Op3) {
>> const MVT *VTs = getNodeValueTypes(VT1, VT2);
>> SDValue Ops[] = { Op1, Op2, Op3 };
>> - return getNode(~Opcode, VTs, 2, Ops, 3).Val;
>> + return getNode(~Opcode, VTs, 2, Ops, 3).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT
>> VT2,
>> const SDValue *Ops, unsigned
>> NumOps) {
>> const MVT *VTs = getNodeValueTypes(VT1, VT2);
>> - return getNode(~Opcode, VTs, 2, Ops, NumOps).Val;
>> + return getNode(~Opcode, VTs, 2, Ops, NumOps).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT
>> VT2, MVT VT3,
>> SDValue Op1, SDValue Op2) {
>> const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
>> SDValue Ops[] = { Op1, Op2 };
>> - return getNode(~Opcode, VTs, 3, Ops, 2).Val;
>> + return getNode(~Opcode, VTs, 3, Ops, 2).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT
>> VT2, MVT VT3,
>> SDValue Op1, SDValue Op2,
>> SDValue Op3) {
>> const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
>> SDValue Ops[] = { Op1, Op2, Op3 };
>> - return getNode(~Opcode, VTs, 3, Ops, 3).Val;
>> + return getNode(~Opcode, VTs, 3, Ops, 3).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT
>> VT2, MVT VT3,
>> const SDValue *Ops, unsigned
>> NumOps) {
>> const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
>> - return getNode(~Opcode, VTs, 3, Ops, NumOps).Val;
>> + return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
>> MVT VT2, MVT VT3, MVT VT4,
>> @@ -4208,14 +4208,14 @@
>> VTList.push_back(VT3);
>> VTList.push_back(VT4);
>> const MVT *VTs = getNodeValueTypes(VTList);
>> - return getNode(~Opcode, VTs, 4, Ops, NumOps).Val;
>> + return getNode(~Opcode, VTs, 4, Ops, NumOps).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
>> const std::vector<MVT> &ResultTys,
>> const SDValue *Ops, unsigned
>> NumOps) {
>> const MVT *VTs = getNodeValueTypes(ResultTys);
>> return getNode(~Opcode, VTs, ResultTys.size(),
>> - Ops, NumOps).Val;
>> + Ops, NumOps).getNode();
>> }
>>
>> /// getNodeIfExists - Get the specified node if it's already
>> available, or
>> @@ -4240,10 +4240,10 @@
>> ///
>> void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To,
>> DAGUpdateListener
>> *UpdateListener) {
>> - SDNode *From = FromN.Val;
>> + SDNode *From = FromN.getNode();
>> assert(From->getNumValues() == 1 && FromN.getResNo() == 0 &&
>> "Cannot replace with this method!");
>> - assert(From != To.Val && "Cannot replace uses of with self");
>> + assert(From != To.getNode() && "Cannot replace uses of with
>> self");
>>
>> while (!From->use_empty()) {
>> SDNode::use_iterator UI = From->use_begin();
>> @@ -4258,7 +4258,7 @@
>> From->removeUser(operandNum, U);
>> *I = To;
>> I->setUser(U);
>> - To.Val->addUser(operandNum, U);
>> + To.getNode()->addUser(operandNum, U);
>> }
>>
>> // Now that we have modified U, add it back to the CSE maps. If
>> it already
>> @@ -4305,7 +4305,7 @@
>> I != E; ++I, ++operandNum)
>> if (I->getVal() == From) {
>> From->removeUser(operandNum, U);
>> - I->getVal() = To;
>> + I->getSDValue().setNode(To);
>> To->addUser(operandNum, U);
>> }
>>
>> @@ -4351,7 +4351,7 @@
>> From->removeUser(operandNum, U);
>> *I = ToOp;
>> I->setUser(U);
>> - ToOp.Val->addUser(operandNum, U);
>> + ToOp.getNode()->addUser(operandNum, U);
>> }
>>
>> // Now that we have modified U, add it back to the CSE maps. If
>> it already
>> @@ -4372,7 +4372,7 @@
>> }
>>
>> /// ReplaceAllUsesOfValueWith - Replace any uses of From with To,
>> leaving
>> -/// uses of other values produced by From.Val alone. The Deleted
>> vector is
>> +/// uses of other values produced by From.getVal() alone. The
>> Deleted vector is
>> /// handled the same way as for ReplaceAllUsesWith.
>> void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue
>> To,
>> DAGUpdateListener
>> *UpdateListener){
>> @@ -4380,14 +4380,14 @@
>> if (From == To) return;
>>
>> // Handle the simple, trivial, case efficiently.
>> - if (From.Val->getNumValues() == 1) {
>> + if (From.getNode()->getNumValues() == 1) {
>> ReplaceAllUsesWith(From, To, UpdateListener);
>> return;
>> }
>>
>> - // Get all of the users of From.Val. We want these in a nice,
>> + // Get all of the users of From.getNode(). We want these in a
>> nice,
>> // deterministically ordered and uniqued set, so we use a
>> SmallSetVector.
>> - SmallSetVector<SDNode*, 16> Users(From.Val->use_begin(), From.Val-
>>> use_end());
>> + SmallSetVector<SDNode*, 16> Users(From.getNode()->use_begin(),
>> From.getNode()->use_end());
>>
>> while (!Users.empty()) {
>> // We know that this user uses some value of From. If it is the
>> right
>> @@ -4410,10 +4410,10 @@
>> // Update all operands that match "From" in case there are
>> multiple uses.
>> for (; Op != E; ++Op) {
>> if (*Op == From) {
>> - From.Val->removeUser(Op-User->op_begin(), User);
>> + From.getNode()->removeUser(Op-User->op_begin(), User);
>> *Op = To;
>> Op->setUser(User);
>> - To.Val->addUser(Op-User->op_begin(), User);
>> + To.getNode()->addUser(Op-User->op_begin(), User);
>> }
>> }
>>
>> @@ -4437,7 +4437,7 @@
>> }
>>
>> /// ReplaceAllUsesOfValuesWith - Replace any uses of From with To,
>> leaving
>> -/// uses of other values produced by From.Val alone. The same
>> value may
>> +/// uses of other values produced by From.getVal() alone. The same
>> value may
>> /// appear in both the From and To list. The Deleted vector is
>> /// handled the same way as for ReplaceAllUsesWith.
>> void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From,
>> @@ -4450,8 +4450,8 @@
>>
>> SmallVector<std::pair<SDNode *, unsigned>, 16> Users;
>> for (unsigned i = 0; i != Num; ++i)
>> - for (SDNode::use_iterator UI = From[i].Val->use_begin(),
>> - E = From[i].Val->use_end(); UI != E; ++UI)
>> + for (SDNode::use_iterator UI = From[i].getNode()->use_begin(),
>> + E = From[i].getNode()->use_end(); UI != E; ++UI)
>> Users.push_back(std::make_pair(*UI, i));
>>
>> while (!Users.empty()) {
>> @@ -4476,10 +4476,10 @@
>> // Update all operands that match "From" in case there are
>> multiple uses.
>> for (; Op != E; ++Op) {
>> if (*Op == From[i]) {
>> - From[i].Val->removeUser(Op-User->op_begin(), User);
>> + From[i].getNode()->removeUser(Op-User->op_begin(), User);
>> *Op = To[i];
>> Op->setUser(User);
>> - To[i].Val->addUser(Op-User->op_begin(), User);
>> + To[i].getNode()->addUser(Op-User->op_begin(), User);
>> }
>> }
>>
>> @@ -4617,7 +4617,7 @@
>>
>> // Check if the memory reference references a frame index
>> const FrameIndexSDNode *FI =
>> - dyn_cast<const FrameIndexSDNode>(getBasePtr().Val);
>> + dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode());
>> if (!getSrcValue() && FI)
>> return MachineMemOperand(PseudoSourceValue::getFixedStack(FI-
>>> getIndex()),
>> Flags, 0, Size, getAlignment());
>> @@ -4746,7 +4746,7 @@
>> return;
>>
>> for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; +
>> +i) {
>> - SDNode *Op = N->getOperand(i).Val;
>> + SDNode *Op = N->getOperand(i).getNode();
>> if (Op == P) {
>> found = true;
>> return;
>> @@ -5115,13 +5115,13 @@
>> OS << " ";
>> for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
>> if (i) OS << ", ";
>> - OS << (void*)getOperand(i).Val;
>> + OS << (void*)getOperand(i).getNode();
>> if (unsigned RN = getOperand(i).getResNo())
>> OS << ":" << RN;
>> }
>>
>> if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) {
>> - SDNode *Mask = getOperand(2).Val;
>> + SDNode *Mask = getOperand(2).getNode();
>> OS << "<";
>> for (unsigned i = 0, e = Mask->getNumOperands(); i != e; ++i) {
>> if (i) OS << ",";
>> @@ -5262,11 +5262,11 @@
>>
>> static void DumpNodes(const SDNode *N, unsigned indent, const
>> SelectionDAG *G) {
>> for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
>> - if (N->getOperand(i).Val->hasOneUse())
>> - DumpNodes(N->getOperand(i).Val, indent+2, G);
>> + if (N->getOperand(i).getNode()->hasOneUse())
>> + DumpNodes(N->getOperand(i).getNode(), indent+2, G);
>> else
>> cerr << "\n" << std::string(indent+2, ' ')
>> - << (void*)N->getOperand(i).Val << ": <multiple use>";
>> + << (void*)N->getOperand(i).getNode() << ": <multiple
>> use>";
>>
>>
>> cerr << "\n" << std::string(indent, ' ');
>> @@ -5279,11 +5279,11 @@
>> for (allnodes_const_iterator I = allnodes_begin(), E =
>> allnodes_end();
>> I != E; ++I) {
>> const SDNode *N = I;
>> - if (!N->hasOneUse() && N != getRoot().Val)
>> + if (!N->hasOneUse() && N != getRoot().getNode())
>> DumpNodes(N, 2, this);
>> }
>>
>> - if (getRoot().Val) DumpNodes(getRoot().Val, 2, this);
>> + if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this);
>>
>> cerr << "\n\n";
>> }
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
>> (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Aug
>> 28 16:40:38 2008
>> @@ -784,8 +784,8 @@
>> if (Root.getOpcode() != ISD::EntryToken) {
>> unsigned i = 0, e = PendingExports.size();
>> for (; i != e; ++i) {
>> - assert(PendingExports[i].Val->getNumOperands() > 1);
>> - if (PendingExports[i].Val->getOperand(0) == Root)
>> + assert(PendingExports[i].getNode()->getNumOperands() > 1);
>> + if (PendingExports[i].getNode()->getOperand(0) == Root)
>> break; // Don't add the root if we already indirectly
>> depend on it.
>> }
>>
>> @@ -824,7 +824,7 @@
>>
>> void setValue(const Value *V, SDValue NewN) {
>> SDValue &N = NodeMap[V];
>> - assert(N.Val == 0 && "Already set a value for this node!");
>> + assert(N.getNode() == 0 && "Already set a value for this
>> node!");
>> N = NewN;
>> }
>>
>> @@ -1286,7 +1286,7 @@
>>
>> SDValue SelectionDAGLowering::getValue(const Value *V) {
>> SDValue &N = NodeMap[V];
>> - if (N.Val) return N;
>> + if (N.getNode()) return N;
>>
>> if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
>> MVT VT = TLI.getValueType(V->getType(), true);
>> @@ -1310,7 +1310,7 @@
>> if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
>> visit(CE->getOpcode(), *CE);
>> SDValue N1 = NodeMap[V];
>> - assert(N1.Val && "visit didn't populate the ValueMap!");
>> + assert(N1.getNode() && "visit didn't populate the ValueMap!");
>> return N1;
>> }
>>
>> @@ -1318,7 +1318,7 @@
>> SmallVector<SDValue, 4> Constants;
>> for (User::const_op_iterator OI = C->op_begin(), OE = C-
>>> op_end();
>> OI != OE; ++OI) {
>> - SDNode *Val = getValue(*OI).Val;
>> + SDNode *Val = getValue(*OI).getNode();
>> for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
>> Constants.push_back(SDValue(Val, i));
>> }
>> @@ -1428,7 +1428,7 @@
>> else if (F->paramHasAttr(0, ParamAttr::ZExt))
>> ExtendKind = ISD::ZERO_EXTEND;
>>
>> - getCopyToParts(DAG, SDValue(RetOp.Val, RetOp.getResNo() + j),
>> + getCopyToParts(DAG, SDValue(RetOp.getNode(), RetOp.getResNo()
>> + j),
>> &Parts[0], NumParts, PartVT, ExtendKind);
>>
>> for (unsigned i = 0; i < NumParts; ++i) {
>> @@ -2855,15 +2855,15 @@
>> // Copy the beginning value(s) from the original aggregate.
>> for (; i != LinearIndex; ++i)
>> Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
>> - SDValue(Agg.Val, Agg.getResNo() + i);
>> + SDValue(Agg.getNode(), Agg.getResNo() + i);
>> // Copy values from the inserted value(s).
>> for (; i != LinearIndex + NumValValues; ++i)
>> Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
>> - SDValue(Val.Val, Val.getResNo() + i - LinearIndex);
>> + SDValue(Val.getNode(), Val.getResNo() + i -
>> LinearIndex);
>> // Copy remaining value(s) from the original aggregate.
>> for (; i != NumAggValues; ++i)
>> Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
>> - SDValue(Agg.Val, Agg.getResNo() + i);
>> + SDValue(Agg.getNode(), Agg.getResNo() + i);
>>
>> setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0],
>> NumAggValues),
>> &Values[0], NumAggValues));
>> @@ -2888,8 +2888,8 @@
>> // Copy out the selected value(s).
>> for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
>> Values[i - LinearIndex] =
>> - OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val-
>>> getValueType(Agg.getResNo() + i)) :
>> - SDValue(Agg.Val, Agg.getResNo() + i);
>> + OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.getNode()-
>>> getValueType(Agg.getResNo() + i)) :
>> + SDValue(Agg.getNode(), Agg.getResNo() + i);
>>
>> setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0],
>> NumValValues),
>> &Values[0], NumValValues));
>> @@ -3084,7 +3084,7 @@
>> bool isVolatile = I.isVolatile();
>> unsigned Alignment = I.getAlignment();
>> for (unsigned i = 0; i != NumValues; ++i)
>> - Chains[i] = DAG.getStore(Root, SDValue(Src.Val, Src.getResNo()
>> + i),
>> + Chains[i] = DAG.getStore(Root, SDValue(Src.getNode(),
>> Src.getResNo() + i),
>> DAG.getNode(ISD::ADD, PtrVT, Ptr,
>> DAG.getConstant(Offsets[i],
>> PtrVT)),
>> PtrV, Offsets[i],
>> @@ -3154,7 +3154,7 @@
>> &Ops[0], Ops.size());
>>
>> if (HasChain) {
>> - SDValue Chain = Result.getValue(Result.Val->getNumValues()-1);
>> + SDValue Chain = Result.getValue(Result.getNode()-
>>> getNumValues()-1);
>> if (OnlyLoad)
>> PendingLoads.push_back(Chain);
>> else
>> @@ -3621,7 +3621,7 @@
>> Value *Alloca = I.getOperand(1);
>> Constant *TypeMap = cast<Constant>(I.getOperand(2));
>>
>> - FrameIndexSDNode *FI =
>> cast<FrameIndexSDNode>(getValue(Alloca).Val);
>> + FrameIndexSDNode *FI =
>> cast<FrameIndexSDNode>(getValue(Alloca).getNode());
>> GFI->addStackRoot(FI->getIndex(), TypeMap);
>> }
>> return 0;
>> @@ -4751,7 +4751,7 @@
>>
>> // Finish up input operands.
>> AsmNodeOperands[0] = Chain;
>> - if (Flag.Val) AsmNodeOperands.push_back(Flag);
>> + if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
>>
>> Chain = DAG.getNode(ISD::INLINEASM,
>> DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
>> @@ -4770,7 +4770,7 @@
>> // bit_convert.
>> if (const StructType *ResSTy =
>> dyn_cast<StructType>(CS.getType())) {
>> for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; +
>> +i) {
>> - if (Val.Val->getValueType(i).isVector())
>> + if (Val.getNode()->getValueType(i).isVector())
>> Val = DAG.getNode(ISD::BIT_CONVERT,
>> TLI.getValueType(ResSTy-
>>> getElementType(i)), Val);
>> }
>> @@ -4963,7 +4963,7 @@
>> // Create the node.
>> SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
>> DAG.getVTList(&RetVals[0],
>> RetVals.size()),
>> - &Ops[0], Ops.size()).Val;
>> + &Ops[0], Ops.size()).getNode();
>>
>> // Prelower FORMAL_ARGUMENTS. This isn't required for
>> functionality, but
>> // allows exposing the loads that may be part of the argument
>> access to the
>> @@ -4972,18 +4972,18 @@
>>
>> // The number of results should match up, except that the lowered
>> one may have
>> // an extra flag result.
>> - assert((Result->getNumValues() == TmpRes.Val->getNumValues() ||
>> - (Result->getNumValues()+1 == TmpRes.Val->getNumValues() &&
>> + assert((Result->getNumValues() == TmpRes.getNode()-
>>> getNumValues() ||
>> + (Result->getNumValues()+1 == TmpRes.getNode()-
>>> getNumValues() &&
>> TmpRes.getValue(Result->getNumValues()).getValueType() ==
>> MVT::Flag))
>> && "Lowering produced unexpected number of results!");
>>
>> // The FORMAL_ARGUMENTS node itself is likely no longer needed.
>> - if (Result != TmpRes.Val && Result->use_empty()) {
>> + if (Result != TmpRes.getNode() && Result->use_empty()) {
>> HandleSDNode Dummy(DAG.getRoot());
>> DAG.RemoveDeadNode(Result);
>> }
>>
>> - Result = TmpRes.Val;
>> + Result = TmpRes.getNode();
>>
>> unsigned NumArgRegs = Result->getNumValues() - 1;
>> DAG.setRoot(SDValue(Result, NumArgRegs));
>> @@ -5044,7 +5044,7 @@
>> Value != NumValues; ++Value) {
>> MVT VT = ValueVTs[Value];
>> const Type *ArgTy = VT.getTypeForMVT();
>> - SDValue Op = SDValue(Args[i].Node.Val,
>> Args[i].Node.getResNo() + Value);
>> + SDValue Op = SDValue(Args[i].Node.getNode(),
>> Args[i].Node.getResNo() + Value);
>> ISD::ArgFlagsTy Flags;
>> unsigned OriginalAlignment =
>> getTargetData()->getABITypeAlignment(ArgTy);
>> @@ -5333,7 +5333,7 @@
>>
>> // Find RET node.
>> if (Terminator.getOpcode() == ISD::RET) {
>> - Ret = Terminator.Val;
>> + Ret = Terminator.getNode();
>> }
>>
>> // Fix tail call attribute of CALL nodes.
>> @@ -5355,8 +5355,8 @@
>> // Not eligible. Mark CALL node as non tail call.
>> SmallVector<SDValue, 32> Ops;
>> unsigned idx=0;
>> - for(SDNode::op_iterator I =OpCall.Val->op_begin(),
>> - E = OpCall.Val->op_end(); I != E; I++, idx++) {
>> + for(SDNode::op_iterator I =OpCall.getNode()->op_begin(),
>> + E = OpCall.getNode()->op_end(); I != E; I++, idx++) {
>> if (idx!=3)
>> Ops.push_back(*I);
>> else
>> @@ -5369,8 +5369,8 @@
>> SmallVector<SDValue, 32> Ops;
>> SDValue Chain = OpCall.getOperand(0), InFlag;
>> unsigned idx=0;
>> - for(SDNode::op_iterator I = OpCall.Val->op_begin(),
>> - E = OpCall.Val->op_end(); I != E; I++, idx++) {
>> + for(SDNode::op_iterator I = OpCall.getNode()->op_begin(),
>> + E = OpCall.getNode()->op_end(); I != E; I++, idx++) {
>> SDValue Arg = *I;
>> if (idx > 4 && (idx % 2)) {
>> bool isByVal =
>> cast<ARG_FLAGSSDNode>(OpCall.getOperand(idx+1))->
>> @@ -5557,7 +5557,7 @@
>> SmallPtrSet<SDNode*, 128> VisitedNodes;
>> SmallVector<SDNode*, 128> Worklist;
>>
>> - Worklist.push_back(CurDAG->getRoot().Val);
>> + Worklist.push_back(CurDAG->getRoot().getNode());
>>
>> APInt Mask;
>> APInt KnownZero;
>> @@ -5574,7 +5574,7 @@
>> // Otherwise, add all chain operands to the worklist.
>> for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
>> if (N->getOperand(i).getValueType() == MVT::Other)
>> - Worklist.push_back(N->getOperand(i).Val);
>> + Worklist.push_back(N->getOperand(i).getNode());
>>
>> // If this is a CopyToReg with a vreg dest, process it.
>> if (N->getOpcode() != ISD::CopyToReg)
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
>> (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp Thu
>> Aug 28 16:40:38 2008
>> @@ -109,8 +109,8 @@
>> static void addCustomGraphFeatures(SelectionDAG *G,
>> GraphWriter<SelectionDAG*>
>> &GW) {
>> GW.emitSimpleNode(0, "plaintext=circle", "GraphRoot");
>> - if (G->getRoot().Val)
>> - GW.emitEdge(0, -1, G->getRoot().Val, G-
>> >getRoot().getResNo(),
>> + if (G->getRoot().getNode())
>> + GW.emitEdge(0, -1, G->getRoot().getNode(), G-
>>> getRoot().getResNo(),
>> "color=blue,style=dashed");
>> }
>> };
>> @@ -356,7 +356,7 @@
>> static void addCustomGraphFeatures(ScheduleDAG *G,
>> GraphWriter<ScheduleDAG*>
>> &GW) {
>> GW.emitSimpleNode(0, "plaintext=circle", "GraphRoot");
>> - const SDNode *N = G->DAG.getRoot().Val;
>> + const SDNode *N = G->DAG.getRoot().getNode();
>> if (N && N->getNodeId() != -1)
>> GW.emitEdge(0, -1, &G->SUnits[N->getNodeId()], -1,
>> "color=blue,style=dashed");
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Aug
>> 28 16:40:38 2008
>> @@ -674,7 +674,7 @@
>> KnownZero = KnownOne = APInt(BitWidth, 0);
>>
>> // Other users may use these bits.
>> - if (!Op.Val->hasOneUse()) {
>> + if (!Op.getNode()->hasOneUse()) {
>> if (Depth != 0) {
>> // If not at the root, Just compute the KnownZero/KnownOne
>> bits to
>> // simplify things downstream.
>> @@ -1131,7 +1131,7 @@
>>
>> // If the input is only used by this truncate, see if we can
>> shrink it based
>> // on the known demanded bits.
>> - if (Op.getOperand(0).Val->hasOneUse()) {
>> + if (Op.getOperand(0).getNode()->hasOneUse()) {
>> SDValue In = Op.getOperand(0);
>> unsigned InBitWidth = In.getValueSizeInBits();
>> switch (In.getOpcode()) {
>> @@ -1259,9 +1259,9 @@
>> case ISD::SETTRUE2: return DAG.getConstant(1, VT);
>> }
>>
>> - if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
>> + if (ConstantSDNode *N1C =
>> dyn_cast<ConstantSDNode>(N1.getNode())) {
>> const APInt &C1 = N1C->getAPIntValue();
>> - if (isa<ConstantSDNode>(N0.Val)) {
>> + if (isa<ConstantSDNode>(N0.getNode())) {
>> return DAG.FoldSetCC(VT, N0, N1, Cond);
>> } else {
>> // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this
>> is an
>> @@ -1356,7 +1356,7 @@
>> DAG.getConstant(Imm, Op0Ty));
>> }
>> if (!DCI.isCalledByLegalizer())
>> - DCI.AddToWorklist(ZextOp.Val);
>> + DCI.AddToWorklist(ZextOp.getNode());
>> // Otherwise, make this a use of a zext.
>> return DAG.getSetCC(VT, ZextOp,
>> DAG.getConstant(C1 & APInt::getLowBitsSet(
>> @@ -1493,16 +1493,16 @@
>> }
>> }
>> }
>> - } else if (isa<ConstantSDNode>(N0.Val)) {
>> + } else if (isa<ConstantSDNode>(N0.getNode())) {
>> // Ensure that the constant occurs on the RHS.
>> return DAG.getSetCC(VT, N1, N0,
>> ISD::getSetCCSwappedOperands(Cond));
>> }
>>
>> - if (isa<ConstantFPSDNode>(N0.Val)) {
>> + if (isa<ConstantFPSDNode>(N0.getNode())) {
>> // Constant fold or commute setcc.
>> SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond);
>> - if (O.Val) return O;
>> - } else if (ConstantFPSDNode *CFP =
>> dyn_cast<ConstantFPSDNode>(N1.Val)) {
>> + if (O.getNode()) return O;
>> + } else if (ConstantFPSDNode *CFP =
>> dyn_cast<ConstantFPSDNode>(N1.getNode())) {
>> // If the RHS of an FP comparison is a constant, simplify it
>> away in
>> // some cases.
>> if (CFP->getValueAPF().isNaN()) {
>> @@ -1564,7 +1564,7 @@
>> if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
>> if (ConstantSDNode *LHSR =
>> dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
>> // Turn (X+C1) == C2 --> X == C2-C1
>> - if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
>> + if (N0.getOpcode() == ISD::ADD && N0.getNode()-
>>> hasOneUse()) {
>> return DAG.getSetCC(VT, N0.getOperand(0),
>> DAG.getConstant(RHSC->getValue()-LHSR-
>>> getValue(),
>> N0.getValueType()), Cond);
>> @@ -1585,7 +1585,7 @@
>>
>> // Turn (C1-X) == C2 --> X == C1-C2
>> if (ConstantSDNode *SUBC =
>> dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
>> - if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
>> + if (N0.getOpcode() == ISD::SUB && N0.getNode()-
>>> hasOneUse()) {
>> return
>> DAG.getSetCC(VT, N0.getOperand(1),
>> DAG.getConstant(SUBC->getAPIntValue() -
>> @@ -1604,14 +1604,14 @@
>> if (DAG.isCommutativeBinOp(N0.getOpcode()))
>> return DAG.getSetCC(VT, N0.getOperand(0),
>> DAG.getConstant(0, N0.getValueType()),
>> Cond);
>> - else if (N0.Val->hasOneUse()) {
>> + else if (N0.getNode()->hasOneUse()) {
>> assert(N0.getOpcode() == ISD::SUB && "Unexpected
>> operation!");
>> // (Z-X) == X --> Z == X<<1
>> SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(),
>> N1,
>> DAG.getConstant(1,
>> getShiftAmountTy()));
>> if (!DCI.isCalledByLegalizer())
>> - DCI.AddToWorklist(SH.Val);
>> + DCI.AddToWorklist(SH.getNode());
>> return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
>> }
>> }
>> @@ -1627,13 +1627,13 @@
>> if (DAG.isCommutativeBinOp(N1.getOpcode())) {
>> return DAG.getSetCC(VT, N1.getOperand(0),
>> DAG.getConstant(0, N1.getValueType()),
>> Cond);
>> - } else if (N1.Val->hasOneUse()) {
>> + } else if (N1.getNode()->hasOneUse()) {
>> assert(N1.getOpcode() == ISD::SUB && "Unexpected
>> operation!");
>> // X == (Z-X) --> X<<1 == Z
>> SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
>> DAG.getConstant(1,
>> getShiftAmountTy()));
>> if (!DCI.isCalledByLegalizer())
>> - DCI.AddToWorklist(SH.Val);
>> + DCI.AddToWorklist(SH.getNode());
>> return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
>> }
>> }
>> @@ -1649,7 +1649,7 @@
>> Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
>> N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1,
>> MVT::i1));
>> if (!DCI.isCalledByLegalizer())
>> - DCI.AddToWorklist(Temp.Val);
>> + DCI.AddToWorklist(Temp.getNode());
>> break;
>> case ISD::SETNE: // X != Y --> (X^Y)
>> N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
>> @@ -1659,21 +1659,21 @@
>> Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1,
>> MVT::i1));
>> N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
>> if (!DCI.isCalledByLegalizer())
>> - DCI.AddToWorklist(Temp.Val);
>> + DCI.AddToWorklist(Temp.getNode());
>> break;
>> case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
>> case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
>> Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1,
>> MVT::i1));
>> N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
>> if (!DCI.isCalledByLegalizer())
>> - DCI.AddToWorklist(Temp.Val);
>> + DCI.AddToWorklist(Temp.getNode());
>> break;
>> case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
>> case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
>> Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1,
>> MVT::i1));
>> N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
>> if (!DCI.isCalledByLegalizer())
>> - DCI.AddToWorklist(Temp.Val);
>> + DCI.AddToWorklist(Temp.getNode());
>> break;
>> case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
>> case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
>> @@ -1683,7 +1683,7 @@
>> }
>> if (VT != MVT::i1) {
>> if (!DCI.isCalledByLegalizer())
>> - DCI.AddToWorklist(N0.Val);
>> + DCI.AddToWorklist(N0.getNode());
>> // FIXME: If running after legalize, we probably can't do this.
>> N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
>> }
>> @@ -1708,13 +1708,13 @@
>> if (N->getOpcode() == ISD::ADD) {
>> SDValue N1 = N->getOperand(0);
>> SDValue N2 = N->getOperand(1);
>> - if (isGAPlusOffset(N1.Val, GA, Offset)) {
>> + if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
>> ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
>> if (V) {
>> Offset += V->getSignExtended();
>> return true;
>> }
>> - } else if (isGAPlusOffset(N2.Val, GA, Offset)) {
>> + } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
>> ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
>> if (V) {
>> Offset += V->getSignExtended();
>> @@ -1732,7 +1732,7 @@
>> bool TargetLowering::isConsecutiveLoad(SDNode *LD, SDNode *Base,
>> unsigned Bytes, int Dist,
>> const MachineFrameInfo *MFI)
>> const {
>> - if (LD->getOperand(0).Val != Base->getOperand(0).Val)
>> + if (LD->getOperand(0).getNode() != Base->getOperand(0).getNode())
>> return false;
>> MVT VT = LD->getValueType(0);
>> if (VT.getSizeInBits() / 8 != Bytes)
>> @@ -1755,8 +1755,8 @@
>> GlobalValue *GV2 = NULL;
>> int64_t Offset1 = 0;
>> int64_t Offset2 = 0;
>> - bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1);
>> - bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2);
>> + bool isGA1 = isGAPlusOffset(Loc.getNode(), GV1, Offset1);
>> + bool isGA2 = isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
>> if (isGA1 && isGA2 && GV1 == GV2)
>> return Offset1 == (Offset2 + Dist*Bytes);
>> return false;
>> @@ -1979,7 +1979,7 @@
>> // For example, on X86 we might have an 'rI' constraint. If the
>> operand
>> // is an integer in the range [0..31] we want to use I (saving a
>> load
>> // of a register), otherwise we must use 'r'.
>> - if (CType == TargetLowering::C_Other && Op.Val) {
>> + if (CType == TargetLowering::C_Other && Op.getNode()) {
>> assert(OpInfo.Codes[i].size() == 1 &&
>> "Unhandled multi-letter 'other' constraint");
>> std::vector<SDValue> ResultOps;
>> @@ -2273,34 +2273,34 @@
>> else if (isOperationLegal(ISD::SMUL_LOHI, VT))
>> Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT),
>> N->getOperand(0),
>> - DAG.getConstant(magics.m, VT)).Val,
>> 1);
>> + DAG.getConstant(magics.m,
>> VT)).getNode(), 1);
>> else
>> return SDValue(); // No mulhs or equvialent
>> // If d > 0 and m < 0, add the numerator
>> if (d > 0 && magics.m < 0) {
>> Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
>> if (Created)
>> - Created->push_back(Q.Val);
>> + Created->push_back(Q.getNode());
>> }
>> // If d < 0 and m > 0, subtract the numerator.
>> if (d < 0 && magics.m > 0) {
>> Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
>> if (Created)
>> - Created->push_back(Q.Val);
>> + Created->push_back(Q.getNode());
>> }
>> // Shift right algebraic if shift value is nonzero
>> if (magics.s > 0) {
>> Q = DAG.getNode(ISD::SRA, VT, Q,
>> DAG.getConstant(magics.s, getShiftAmountTy()));
>> if (Created)
>> - Created->push_back(Q.Val);
>> + Created->push_back(Q.getNode());
>> }
>> // Extract the sign bit and add it to the quotient
>> SDValue T =
>> DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
>> getShiftAmountTy()));
>> if (Created)
>> - Created->push_back(T.Val);
>> + Created->push_back(T.getNode());
>> return DAG.getNode(ISD::ADD, VT, Q, T);
>> }
>>
>> @@ -2327,11 +2327,11 @@
>> else if (isOperationLegal(ISD::UMUL_LOHI, VT))
>> Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT),
>> N->getOperand(0),
>> - DAG.getConstant(magics.m, VT)).Val,
>> 1);
>> + DAG.getConstant(magics.m,
>> VT)).getNode(), 1);
>> else
>> return SDValue(); // No mulhu or equvialent
>> if (Created)
>> - Created->push_back(Q.Val);
>> + Created->push_back(Q.getNode());
>>
>> if (magics.a == 0) {
>> return DAG.getNode(ISD::SRL, VT, Q,
>> @@ -2339,14 +2339,14 @@
>> } else {
>> SDValue NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
>> if (Created)
>> - Created->push_back(NPQ.Val);
>> + Created->push_back(NPQ.getNode());
>> NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
>> DAG.getConstant(1, getShiftAmountTy()));
>> if (Created)
>> - Created->push_back(NPQ.Val);
>> + Created->push_back(NPQ.getNode());
>> NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
>> if (Created)
>> - Created->push_back(NPQ.Val);
>> + Created->push_back(NPQ.getNode());
>> return DAG.getNode(ISD::SRL, VT, NPQ,
>> DAG.getConstant(magics.s-1,
>> getShiftAmountTy()));
>> }
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -529,7 +529,7 @@
>>
>>
>> SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
>> - SDNode *N = Op.Val;
>> + SDNode *N = Op.getNode();
>>
>> if (N->isMachineOpcode())
>> return NULL; // Already selected.
>> @@ -729,11 +729,11 @@
>> SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
>> SDNode *ResNode = CurDAG->getTargetNode(Opc, MVT::Other,
>> MVT::Flag, Ops, 5);
>> Chain = SDValue(ResNode, 0);
>> - if (Op.Val->getNumValues() == 2) {
>> + if (Op.getNode()->getNumValues() == 2) {
>> InFlag = SDValue(ResNode, 1);
>> - ReplaceUses(SDValue(Op.Val, 1), InFlag);
>> + ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
>> }
>> - ReplaceUses(SDValue(Op.Val, 0), SDValue(Chain.Val,
>> Chain.getResNo()));
>> + ReplaceUses(SDValue(Op.getNode(), 0), SDValue(Chain.getNode(),
>> Chain.getResNo()));
>> return NULL;
>> }
>> case ARMISD::CMOV: {
>> @@ -763,7 +763,7 @@
>> SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
>> cast<ConstantSDNode>(N2)-
>>> getValue()), MVT::i32);
>> SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3,
>> InFlag };
>> - return CurDAG->SelectNodeTo(Op.Val, ARM::MOVCCs, MVT::i32,
>> Ops, 7);
>> + return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCs,
>> MVT::i32, Ops, 7);
>> }
>>
>> // Pattern: (ARMcmov:i32 GPR:i32:$false,
>> @@ -774,16 +774,16 @@
>> // Pattern complexity = 10 cost = 1 size = 0
>> if (VT == MVT::i32 &&
>> N3.getOpcode() == ISD::Constant &&
>> - Predicate_so_imm(N3.Val)) {
>> + Predicate_so_imm(N3.getNode())) {
>> AddToISelQueue(N0);
>> AddToISelQueue(InFlag);
>> SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
>> cast<ConstantSDNode>(N1)-
>>> getValue()), MVT::i32);
>> - Tmp1 = Transform_so_imm_XFORM(Tmp1.Val);
>> + Tmp1 = Transform_so_imm_XFORM(Tmp1.getNode());
>> SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
>> cast<ConstantSDNode>(N2)-
>>> getValue()), MVT::i32);
>> SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
>> - return CurDAG->SelectNodeTo(Op.Val, ARM::MOVCCi, MVT::i32,
>> Ops, 5);
>> + return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCi,
>> MVT::i32, Ops, 5);
>> }
>>
>> // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true,
>> (imm:i32):$cc)
>> @@ -815,7 +815,7 @@
>> Opc = ARM::FCPYDcc;
>> break;
>> }
>> - return CurDAG->SelectNodeTo(Op.Val, Opc, VT, Ops, 5);
>> + return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
>> }
>> case ARMISD::CNEG: {
>> MVT VT = Op.getValueType();
>> @@ -844,7 +844,7 @@
>> Opc = ARM::FNEGDcc;
>> break;
>> }
>> - return CurDAG->SelectNodeTo(Op.Val, Opc, VT, Ops, 5);
>> + return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
>> }
>> }
>> return SelectCode(Op);
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -400,7 +400,7 @@
>> /// ARMISD:CALL <- callseq_end chain. Also add input and output
>> parameter
>> /// nodes.
>> SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
>> - MVT RetVT= Op.Val->getValueType(0);
>> + MVT RetVT= Op.getNode()->getValueType(0);
>> SDValue Chain = Op.getOperand(0);
>> unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))-
>>> getValue();
>> assert((CallConv == CallingConv::C ||
>> @@ -597,7 +597,7 @@
>> Ops.push_back(DAG.getRegister(RegsToPass[i].first,
>>
>> RegsToPass[i].second.getValueType()));
>>
>> - if (InFlag.Val)
>> + if (InFlag.getNode())
>> Ops.push_back(InFlag);
>> // Returns a chain and a flag for retval copy to use.
>> Chain = DAG.getNode(CallOpc, DAG.getVTList(MVT::Other, MVT::Flag),
>> @@ -621,7 +621,7 @@
>> case MVT::i32:
>> Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32,
>> InFlag).getValue(1);
>> ResultVals.push_back(Chain.getValue(0));
>> - if (Op.Val->getValueType(1) == MVT::i32) {
>> + if (Op.getNode()->getValueType(1) == MVT::i32) {
>> // Returns a i64 value.
>> Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32,
>> Chain.getValue(2)).getValue(1);
>> @@ -981,7 +981,7 @@
>> unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
>> unsigned NumGPRs = 0; // GPRs used for parameter passing.
>>
>> - unsigned NumArgs = Op.Val->getNumValues()-1;
>> + unsigned NumArgs = Op.getNode()->getNumValues()-1;
>> for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo)
>> ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, ArgNo,
>> NumGPRs, ArgOffset));
>> @@ -1029,7 +1029,7 @@
>> ArgValues.push_back(Root);
>>
>> // Return the new list of results.
>> - return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
>> + return DAG.getMergeValues(Op.getNode()->getVTList(),
>> &ArgValues[0],
>> ArgValues.size());
>> }
>>
>> @@ -1037,7 +1037,7 @@
>> static bool isFloatingPointZero(SDValue Op) {
>> if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
>> return CFP->getValueAPF().isPosZero();
>> - else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
>> + else if (ISD::isEXTLoad(Op.getNode()) ||
>> ISD::isNON_EXTLoad(Op.getNode())) {
>> // Maybe this has already been legalized into the constant pool?
>> if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
>> SDValue WrapperOp = Op.getOperand(1).getOperand(0);
>> @@ -1058,7 +1058,7 @@
>> /// the given operands.
>> static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
>> SDValue &ARMCC, SelectionDAG &DAG, bool
>> isThumb) {
>> - if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.Val)) {
>> + if (ConstantSDNode *RHSC =
>> dyn_cast<ConstantSDNode>(RHS.getNode())) {
>> unsigned C = RHSC->getValue();
>> if (!isLegalCmpImmediate(C, isThumb)) {
>> // Constant does not fit, try adjusting it by one?
>> @@ -1362,7 +1362,7 @@
>> &Op, 1);
>>
>> // Merge the pieces into a single i64 value.
>> - return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt,
>> Cvt.getValue(1)).Val;
>> + return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt,
>> Cvt.getValue(1)).getNode();
>> }
>>
>> static SDNode *ExpandSRx(SDNode *N, SelectionDAG &DAG, const
>> ARMSubtarget *ST) {
>> @@ -1393,7 +1393,7 @@
>> Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1));
>>
>> // Merge the pieces into a single i64 value.
>> - return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi).Val;
>> + return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi).getNode();
>> }
>>
>>
>> @@ -1424,9 +1424,9 @@
>>
>>
>> // FIXME: Remove these when LegalizeDAGTypes lands.
>> - case ISD::BIT_CONVERT: return SDValue(ExpandBIT_CONVERT(Op.Val,
>> DAG), 0);
>> + case ISD::BIT_CONVERT: return
>> SDValue(ExpandBIT_CONVERT(Op.getNode(), DAG), 0);
>> case ISD::SRL:
>> - case ISD::SRA: return SDValue(ExpandSRx(Op.Val,
>> DAG,Subtarget),0);
>> + case ISD::SRA: return SDValue(ExpandSRx(Op.getNode(),
>> DAG,Subtarget),0);
>> }
>> return SDValue();
>> }
>> @@ -1734,7 +1734,7 @@
>> return false;
>>
>> bool isInc;
>> - bool isLegal = getIndexedAddressParts(Ptr.Val, VT, isSEXTLoad,
>> Base, Offset,
>> + bool isLegal = getIndexedAddressParts(Ptr.getNode(), VT,
>> isSEXTLoad, Base, Offset,
>> isInc, DAG);
>> if (isLegal) {
>> AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
>>
>> Modified: llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp (original)
>> +++ llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -75,7 +75,7 @@
>> Result |= 1 << i;
>> if (((Constant >> 8*i) & 0xFF) == 0xFF) {
>> // If the entire byte is set, zapnot the byte.
>> - } else if (LHS.Val == 0) {
>> + } else if (LHS.getNode() == 0) {
>> // Otherwise, if the mask was previously validated, we
>> know its okay
>> // to zapnot this entire byte even though all the bits
>> aren't set.
>> } else {
>> @@ -242,7 +242,7 @@
>> // Select - Convert the specified operand from a target-independent
>> to a
>> // target-specific node if it hasn't already been changed.
>> SDNode *AlphaDAGToDAGISel::Select(SDValue Op) {
>> - SDNode *N = Op.Val;
>> + SDNode *N = Op.getNode();
>> if (N->isMachineOpcode()) {
>> return NULL; // Already selected.
>> }
>> @@ -345,7 +345,7 @@
>> }
>>
>> case ISD::SETCC:
>> - if (N->getOperand(0).Val->getValueType(0).isFloatingPoint()) {
>> + if (N->getOperand(0).getNode()-
>>> getValueType(0).isFloatingPoint()) {
>> ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))-
>>> get();
>>
>> unsigned Opc = Alpha::WTF;
>> @@ -460,7 +460,7 @@
>> void AlphaDAGToDAGISel::SelectCALL(SDValue Op) {
>> //TODO: add flag stuff to prevent nondeturministic breakage!
>>
>> - SDNode *N = Op.Val;
>> + SDNode *N = Op.getNode();
>> SDValue Chain = N->getOperand(0);
>> SDValue Addr = N->getOperand(1);
>> SDValue InFlag(0,0); // Null incoming flag value.
>>
>> Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -215,7 +215,7 @@
>> unsigned args_float[] = {
>> Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20,
>> Alpha::F21};
>>
>> - for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo !=
>> e; ++ArgNo) {
>> + for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1;
>> ArgNo != e; ++ArgNo) {
>> SDValue argt;
>> MVT ObjectVT = Op.getValue(ArgNo).getValueType();
>> SDValue ArgVal;
>> @@ -255,7 +255,7 @@
>> // If the functions takes variable number of arguments, copy all
>> regs to stack
>> bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))-
>>> getValue() != 0;
>> if (isVarArg) {
>> - VarArgsOffset = (Op.Val->getNumValues()-1) * 8;
>> + VarArgsOffset = (Op.getNode()->getNumValues()-1) * 8;
>> std::vector<SDValue> LS;
>> for (int i = 0; i < 6; ++i) {
>> if (TargetRegisterInfo::isPhysicalRegister(args_int[i]))
>> @@ -281,7 +281,7 @@
>> ArgValues.push_back(Root);
>>
>> // Return the new list of results.
>> - return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
>> + return DAG.getMergeValues(Op.getNode()->getVTList(),
>> &ArgValues[0],
>> ArgValues.size());
>> }
>>
>> @@ -491,10 +491,10 @@
>> case ISD::SREM:
>> //Expand only on constant case
>> if (Op.getOperand(1).getOpcode() == ISD::Constant) {
>> - MVT VT = Op.Val->getValueType(0);
>> - SDValue Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
>> - BuildUDIV(Op.Val, DAG, NULL) :
>> - BuildSDIV(Op.Val, DAG, NULL);
>> + MVT VT = Op.getNode()->getValueType(0);
>> + SDValue Tmp1 = Op.getNode()->getOpcode() == ISD::UREM ?
>> + BuildUDIV(Op.getNode(), DAG, NULL) :
>> + BuildSDIV(Op.getNode(), DAG, NULL);
>> Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
>> Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
>> return Tmp1;
>> @@ -504,8 +504,8 @@
>> case ISD::UDIV:
>> if (Op.getValueType().isInteger()) {
>> if (Op.getOperand(1).getOpcode() == ISD::Constant)
>> - return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG,
>> NULL)
>> - : BuildUDIV(Op.Val, DAG, NULL);
>> + return Op.getOpcode() == ISD::SDIV ?
>> BuildSDIV(Op.getNode(), DAG, NULL)
>> + : BuildUDIV(Op.getNode(), DAG, NULL);
>> const char* opstr = 0;
>> switch (Op.getOpcode()) {
>> case ISD::UREM: opstr = "__remqu"; break;
>> @@ -522,7 +522,7 @@
>>
>> case ISD::VAARG: {
>> SDValue Chain, DataPtr;
>> - LowerVAARG(Op.Val, Chain, DataPtr, DAG);
>> + LowerVAARG(Op.getNode(), Chain, DataPtr, DAG);
>>
>> SDValue Result;
>> if (Op.getValueType() == MVT::i32)
>> @@ -578,7 +578,7 @@
>>
>> SDValue Chain, DataPtr;
>> LowerVAARG(N, Chain, DataPtr, DAG);
>> - return DAG.getLoad(N->getValueType(0), Chain, DataPtr, NULL,
>> 0).Val;
>> + return DAG.getLoad(N->getValueType(0), Chain, DataPtr, NULL,
>> 0).getNode();
>> }
>>
>>
>>
>> Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original)
>> +++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -579,7 +579,7 @@
>> */
>> SDNode *
>> SPUDAGToDAGISel::Select(SDValue Op) {
>> - SDNode *N = Op.Val;
>> + SDNode *N = Op.getNode();
>> unsigned Opc = N->getOpcode();
>> int n_ops = -1;
>> unsigned NewOpc;
>> @@ -669,9 +669,9 @@
>> MVT VT = Op.getValueType();
>>
>> DEBUG(cerr << "CellSPU: IndirectAddr(LDRESULT, imm):\nOp0 = ");
>> - DEBUG(Op.getOperand(0).Val->dump(CurDAG));
>> + DEBUG(Op.getOperand(0).getNode()->dump(CurDAG));
>> DEBUG(cerr << "\nOp1 = ");
>> - DEBUG(Op.getOperand(1).Val->dump(CurDAG));
>> + DEBUG(Op.getOperand(1).getNode()->dump(CurDAG));
>> DEBUG(cerr << "\n");
>>
>> if (Op1.getOpcode() == ISD::Constant) {
>>
>> Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -503,7 +503,7 @@
>> SDValue chain = LSN->getChain();
>>
>> if (basePtr.getOpcode() == ISD::ADD) {
>> - SDValue Op1 = basePtr.Val->getOperand(1);
>> + SDValue Op1 = basePtr.getNode()->getOperand(1);
>>
>> if (Op1.getOpcode() == ISD::Constant || Op1.getOpcode() ==
>> ISD::TargetConstant) {
>> const ConstantSDNode *CN =
>> cast<ConstantSDNode>(basePtr.getOperand(1));
>> @@ -579,7 +579,7 @@
>> LoadSDNode *LN = cast<LoadSDNode>(Op);
>> SDValue the_chain = LN->getChain();
>> MVT VT = LN->getMemoryVT();
>> - MVT OpVT = Op.Val->getValueType(0);
>> + MVT OpVT = Op.getNode()->getValueType(0);
>> ISD::LoadExtType ExtType = LN->getExtensionType();
>> unsigned alignment = LN->getAlignment();
>> SDValue Ops[8];
>> @@ -591,7 +591,7 @@
>> SDValue result =
>> AlignedLoad(Op, DAG, ST, LN,alignment, offset, rotamt, VT,
>> was16aligned);
>>
>> - if (result.Val == 0)
>> + if (result.getNode() == 0)
>> return result;
>>
>> the_chain = result.getValue(1);
>> @@ -708,7 +708,7 @@
>> AlignedLoad(Op, DAG, ST, SN, alignment,
>> chunk_offset, slot_offset, VT, was16aligned);
>>
>> - if (alignLoadVec.Val == 0)
>> + if (alignLoadVec.getNode() == 0)
>> return alignLoadVec;
>>
>> LoadSDNode *LN = cast<LoadSDNode>(alignLoadVec);
>> @@ -736,7 +736,7 @@
>> // Otherwise generate a D-form address with the slot offset
>> relative
>> // to the stack pointer, which is always aligned.
>> DEBUG(cerr << "CellSPU LowerSTORE: basePtr = ");
>> - DEBUG(basePtr.Val->dump(&DAG));
>> + DEBUG(basePtr.getNode()->dump(&DAG));
>> DEBUG(cerr << "\n");
>>
>> if (basePtr.getOpcode() == SPUISD::IndirectAddr ||
>> @@ -859,7 +859,7 @@
>> static SDValue
>> LowerConstant(SDValue Op, SelectionDAG &DAG) {
>> MVT VT = Op.getValueType();
>> - ConstantSDNode *CN = cast<ConstantSDNode>(Op.Val);
>> + ConstantSDNode *CN = cast<ConstantSDNode>(Op.getNode());
>>
>> if (VT == MVT::i64) {
>> SDValue T = DAG.getConstant(CN->getValue(), MVT::i64);
>> @@ -880,7 +880,7 @@
>> static SDValue
>> LowerConstantFP(SDValue Op, SelectionDAG &DAG) {
>> MVT VT = Op.getValueType();
>> - ConstantFPSDNode *FP = cast<ConstantFPSDNode>(Op.Val);
>> + ConstantFPSDNode *FP = cast<ConstantFPSDNode>(Op.getNode());
>>
>> assert((FP != 0) &&
>> "LowerConstantFP: Node is not ConstantFPSDNode");
>> @@ -932,7 +932,7 @@
>> MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
>>
>> // Add DAG nodes to load the arguments or copy them out of
>> registers.
>> - for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo !=
>> e; ++ArgNo) {
>> + for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1;
>> ArgNo != e; ++ArgNo) {
>> SDValue ArgVal;
>> bool needsLoad = false;
>> MVT ObjectVT = Op.getValue(ArgNo).getValueType();
>> @@ -1061,7 +1061,7 @@
>> ArgValues.push_back(Root);
>>
>> // Return the new list of results.
>> - return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
>> + return DAG.getMergeValues(Op.getNode()->getVTList(),
>> &ArgValues[0],
>> ArgValues.size());
>> }
>>
>> @@ -1076,7 +1076,7 @@
>> (Addr << 14 >> 14) != Addr)
>> return 0; // Top 14 bits have to be sext of immediate.
>>
>> - return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val;
>> + return DAG.getConstant((int)C->getValue() >> 2,
>> MVT::i32).getNode();
>> }
>>
>> static
>> @@ -1226,7 +1226,7 @@
>> Ops.push_back(DAG.getRegister(RegsToPass[i].first,
>>
>> RegsToPass[i].second.getValueType()));
>>
>> - if (InFlag.Val)
>> + if (InFlag.getNode())
>> Ops.push_back(InFlag);
>> // Returns a chain and a flag for retval copy to use.
>> Chain = DAG.getNode(CallOpc, DAG.getVTList(MVT::Other, MVT::Flag),
>> @@ -1237,18 +1237,18 @@
>> DAG.getConstant(NumStackBytes, PtrVT),
>> DAG.getConstant(0, PtrVT),
>> InFlag);
>> - if (Op.Val->getValueType(0) != MVT::Other)
>> + if (Op.getNode()->getValueType(0) != MVT::Other)
>> InFlag = Chain.getValue(1);
>>
>> SDValue ResultVals[3];
>> unsigned NumResults = 0;
>>
>> // If the call has results, copy the values out of the ret val
>> registers.
>> - switch (Op.Val->getValueType(0).getSimpleVT()) {
>> + switch (Op.getNode()->getValueType(0).getSimpleVT()) {
>> default: assert(0 && "Unexpected ret value!");
>> case MVT::Other: break;
>> case MVT::i32:
>> - if (Op.Val->getValueType(1) == MVT::i32) {
>> + if (Op.getNode()->getValueType(1) == MVT::i32) {
>> Chain = DAG.getCopyFromReg(Chain, SPU::R4, MVT::i32,
>> InFlag).getValue(1);
>> ResultVals[0] = Chain.getValue(0);
>> Chain = DAG.getCopyFromReg(Chain, SPU::R3, MVT::i32,
>> @@ -1268,7 +1268,7 @@
>> break;
>> case MVT::f32:
>> case MVT::f64:
>> - Chain = DAG.getCopyFromReg(Chain, SPU::R3, Op.Val-
>>> getValueType(0),
>> + Chain = DAG.getCopyFromReg(Chain, SPU::R3, Op.getNode()-
>>> getValueType(0),
>> InFlag).getValue(1);
>> ResultVals[0] = Chain.getValue(0);
>> NumResults = 1;
>> @@ -1278,7 +1278,7 @@
>> case MVT::v4i32:
>> case MVT::v8i16:
>> case MVT::v16i8:
>> - Chain = DAG.getCopyFromReg(Chain, SPU::R3, Op.Val-
>>> getValueType(0),
>> + Chain = DAG.getCopyFromReg(Chain, SPU::R3, Op.getNode()-
>>> getValueType(0),
>> InFlag).getValue(1);
>> ResultVals[0] = Chain.getValue(0);
>> NumResults = 1;
>> @@ -1301,7 +1301,7 @@
>> unsigned CC = DAG.getMachineFunction().getFunction()-
>>> getCallingConv();
>> bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
>> CCState CCInfo(CC, isVarArg, TM, RVLocs);
>> - CCInfo.AnalyzeReturn(Op.Val, RetCC_SPU);
>> + CCInfo.AnalyzeReturn(Op.getNode(), RetCC_SPU);
>>
>> // If this is the first return lowered for this function, add the
>> regs to the
>> // liveout set for the function.
>> @@ -1321,7 +1321,7 @@
>> Flag = Chain.getValue(1);
>> }
>>
>> - if (Flag.Val)
>> + if (Flag.getNode())
>> return DAG.getNode(SPUISD::RET_FLAG, MVT::Other, Chain, Flag);
>> else
>> return DAG.getNode(SPUISD::RET_FLAG, MVT::Other, Chain);
>> @@ -1339,13 +1339,13 @@
>> // Check to see if this buildvec has a single non-undef value in
>> its elements.
>> for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
>> if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
>> - if (OpVal.Val == 0)
>> + if (OpVal.getNode() == 0)
>> OpVal = N->getOperand(i);
>> else if (OpVal != N->getOperand(i))
>> return 0;
>> }
>>
>> - if (OpVal.Val != 0) {
>> + if (OpVal.getNode() != 0) {
>> if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
>> return CN;
>> }
>> @@ -1599,7 +1599,7 @@
>> uint64_t UndefBits[2];
>> uint64_t SplatBits, SplatUndef;
>> int SplatSize;
>> - if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)
>> + if (GetConstantBuildVectorBits(Op.getNode(), VectorBits,
>> UndefBits)
>> || !isConstantSplat(VectorBits, UndefBits,
>> VT.getVectorElementType().getSizeInBits(),
>> SplatBits, SplatUndef, SplatSize))
>> @@ -1842,11 +1842,11 @@
>> static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
>> SDValue Op0 = Op.getOperand(0); // Op0 = the
>> scalar
>>
>> - if (Op0.Val->getOpcode() == ISD::Constant) {
>> + if (Op0.getNode()->getOpcode() == ISD::Constant) {
>> // For a constant, build the appropriate constant vector, which
>> will
>> // eventually simplify to a vector register load.
>>
>> - ConstantSDNode *CN = cast<ConstantSDNode>(Op0.Val);
>> + ConstantSDNode *CN = cast<ConstantSDNode>(Op0.getNode());
>> SmallVector<SDValue, 16> ConstVecValues;
>> MVT VT;
>> size_t n_copies;
>> @@ -2447,25 +2447,25 @@
>>
>> ConstVec = Op.getOperand(0);
>> Arg = Op.getOperand(1);
>> - if (ConstVec.Val->getOpcode() != ISD::BUILD_VECTOR) {
>> - if (ConstVec.Val->getOpcode() == ISD::BIT_CONVERT) {
>> + if (ConstVec.getNode()->getOpcode() != ISD::BUILD_VECTOR) {
>> + if (ConstVec.getNode()->getOpcode() == ISD::BIT_CONVERT) {
>> ConstVec = ConstVec.getOperand(0);
>> } else {
>> ConstVec = Op.getOperand(1);
>> Arg = Op.getOperand(0);
>> - if (ConstVec.Val->getOpcode() == ISD::BIT_CONVERT) {
>> + if (ConstVec.getNode()->getOpcode() == ISD::BIT_CONVERT) {
>> ConstVec = ConstVec.getOperand(0);
>> }
>> }
>> }
>>
>> - if (ConstVec.Val->getOpcode() == ISD::BUILD_VECTOR) {
>> + if (ConstVec.getNode()->getOpcode() == ISD::BUILD_VECTOR) {
>> uint64_t VectorBits[2];
>> uint64_t UndefBits[2];
>> uint64_t SplatBits, SplatUndef;
>> int SplatSize;
>>
>> - if (!GetConstantBuildVectorBits(ConstVec.Val, VectorBits,
>> UndefBits)
>> + if (!GetConstantBuildVectorBits(ConstVec.getNode(), VectorBits,
>> UndefBits)
>> && isConstantSplat(VectorBits, UndefBits,
>> VT.getVectorElementType().getSizeInBits(),
>> SplatBits, SplatUndef, SplatSize)) {
>> @@ -2477,7 +2477,7 @@
>> for (size_t i = 0; i < tcVecSize; ++i)
>> tcVec[i] = tc;
>>
>> - return DAG.getNode(Op.Val->getOpcode(), VT, Arg,
>> + return DAG.getNode(Op.getNode()->getOpcode(), VT, Arg,
>> DAG.getNode(ISD::BUILD_VECTOR, VT, tcVec,
>> tcVecSize));
>> }
>> }
>> @@ -2632,8 +2632,8 @@
>> default: {
>> cerr << "SPUTargetLowering::LowerOperation(): need to lower this!
>> \n";
>> cerr << "Op.getOpcode() = " << Opc << "\n";
>> - cerr << "*Op.Val:\n";
>> - Op.Val->dump();
>> + cerr << "*Op.getNode():\n";
>> + Op.getNode()->dump();
>> abort();
>> }
>> case ISD::LOAD:
>> @@ -2796,7 +2796,7 @@
>> DEBUG(cerr << "Replace: ");
>> DEBUG(N->dump(&DAG));
>> DEBUG(cerr << "\nWith: ");
>> - DEBUG(Op0.Val->dump(&DAG));
>> + DEBUG(Op0.getNode()->dump(&DAG));
>> DEBUG(cerr << "\n");
>>
>> return Op0;
>> @@ -2813,7 +2813,7 @@
>> DEBUG(cerr << "Replace: ");
>> DEBUG(N->dump(&DAG));
>> DEBUG(cerr << "\nWith: ");
>> - DEBUG(Op0.Val->dump(&DAG));
>> + DEBUG(Op0.getNode()->dump(&DAG));
>> DEBUG(cerr << "\n");
>>
>> return Op0;
>> @@ -2871,11 +2871,11 @@
>> }
>> // Otherwise, return unchanged.
>> #if 1
>> - if (Result.Val) {
>> + if (Result.getNode()) {
>> DEBUG(cerr << "\nReplace.SPU: ");
>> DEBUG(N->dump(&DAG));
>> DEBUG(cerr << "\nWith: ");
>> - DEBUG(Result.Val->dump(&DAG));
>> + DEBUG(Result.getNode()->dump(&DAG));
>> DEBUG(cerr << "\n");
>> }
>> #endif
>>
>> Modified: llvm/trunk/lib/Target/CellSPU/SPUOperands.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUOperands.td?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/CellSPU/SPUOperands.td (original)
>> +++ llvm/trunk/lib/Target/CellSPU/SPUOperands.td Thu Aug 28 16:40:38
>> 2008
>> @@ -24,13 +24,13 @@
>> && "LO16_vec got something other than a BUILD_VECTOR");
>>
>> // Get first constant operand...
>> - for (unsigned i = 0, e = N->getNumOperands(); OpVal.Val == 0 &&
>> i != e; ++i) {
>> + for (unsigned i = 0, e = N->getNumOperands(); OpVal.getNode() ==
>> 0 && i != e; ++i) {
>> if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
>> - if (OpVal.Val == 0)
>> + if (OpVal.getNode() == 0)
>> OpVal = N->getOperand(i);
>> }
>>
>> - assert(OpVal.Val != 0 && "LO16_vec did not locate a <defined>
>> node");
>> + assert(OpVal.getNode() != 0 && "LO16_vec did not locate a
>> <defined> node");
>> ConstantSDNode *CN = cast<ConstantSDNode>(OpVal);
>> return getI32Imm((unsigned)CN->getValue() & 0xffff);
>> }]>;
>> @@ -49,13 +49,13 @@
>> && "HI16_vec got something other than a BUILD_VECTOR");
>>
>> // Get first constant operand...
>> - for (unsigned i = 0, e = N->getNumOperands(); OpVal.Val == 0 &&
>> i != e; ++i) {
>> + for (unsigned i = 0, e = N->getNumOperands(); OpVal.getNode() ==
>> 0 && i != e; ++i) {
>> if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
>> - if (OpVal.Val == 0)
>> + if (OpVal.getNode() == 0)
>> OpVal = N->getOperand(i);
>> }
>>
>> - assert(OpVal.Val != 0 && "HI16_vec did not locate a <defined>
>> node");
>> + assert(OpVal.getNode() != 0 && "HI16_vec did not locate a
>> <defined> node");
>> ConstantSDNode *CN = cast<ConstantSDNode>(OpVal);
>> return getI32Imm((unsigned)CN->getValue() >> 16);
>> }]>;
>> @@ -244,7 +244,7 @@
>> // incoming constant being a 16-bit quantity, where the upper and
>> lower bytes
>> // are EXACTLY the same (e.g., 0x2a2a)
>> def v16i8SExt8Imm: PatLeaf<(build_vector), [{
>> - return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).Val != 0;
>> + return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).getNode() != 0;
>> }], v16i8SExt8Imm_xform>;
>>
>> // v16i8U8Imm_xform function: convert build_vector to unsigned 8-bit
>> @@ -259,7 +259,7 @@
>> // incoming constant being a 16-bit quantity, where the upper and
>> lower bytes
>> // are EXACTLY the same (e.g., 0x2a2a)
>> def v16i8U8Imm: PatLeaf<(build_vector), [{
>> - return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).Val != 0;
>> + return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).getNode() != 0;
>> }], v16i8U8Imm_xform>;
>>
>> // v8i16SExt8Imm_xform function: convert build_vector to 8-bit sign
>> extended
>> @@ -271,7 +271,7 @@
>> // v8i16SExt8Imm: Predicate test for 8-bit sign extended immediate
>> constant
>> // load, works in conjunction with its transform function.
>> def v8i16SExt8Imm: PatLeaf<(build_vector), [{
>> - return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16).Val != 0;
>> + return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16).getNode() != 0;
>> }], v8i16SExt8Imm_xform>;
>>
>> // v8i16SExt10Imm_xform function: convert build_vector to 16-bit
>> sign extended
>> @@ -283,7 +283,7 @@
>> // v8i16SExt10Imm: Predicate test for 16-bit sign extended immediate
>> constant
>> // load, works in conjunction with its transform function.
>> def v8i16SExt10Imm: PatLeaf<(build_vector), [{
>> - return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0;
>> + return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).getNode() != 0;
>> }], v8i16SExt10Imm_xform>;
>>
>> // v8i16Uns10Imm_xform function: convert build_vector to 16-bit
>> unsigned
>> @@ -295,7 +295,7 @@
>> // v8i16Uns10Imm: Predicate test for 16-bit unsigned immediate
>> constant
>> // load, works in conjunction with its transform function.
>> def v8i16Uns10Imm: PatLeaf<(build_vector), [{
>> - return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0;
>> + return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).getNode() != 0;
>> }], v8i16Uns10Imm_xform>;
>>
>> // v8i16SExt16Imm_xform function: convert build_vector to 16-bit
>> sign extended
>> @@ -307,7 +307,7 @@
>> // v8i16SExt16Imm: Predicate test for 16-bit sign extended immediate
>> constant
>> // load, works in conjunction with its transform function.
>> def v8i16SExt16Imm: PatLeaf<(build_vector), [{
>> - return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16).Val != 0;
>> + return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16).getNode() != 0;
>> }], v8i16Uns16Imm_xform>;
>>
>> // v4i32SExt10Imm_xform function: convert build_vector to 10-bit
>> sign extended
>> @@ -319,7 +319,7 @@
>> // v4i32SExt10Imm: Predicate test for 10-bit sign extended immediate
>> constant
>> // load, works in conjunction with its transform function.
>> def v4i32SExt10Imm: PatLeaf<(build_vector), [{
>> - return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0;
>> + return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).getNode() != 0;
>> }], v4i32SExt10Imm_xform>;
>>
>> // v4i32Uns10Imm_xform function: convert build_vector to 10-bit
>> unsigned
>> @@ -331,7 +331,7 @@
>> // v4i32Uns10Imm: Predicate test for 10-bit unsigned immediate
>> constant
>> // load, works in conjunction with its transform function.
>> def v4i32Uns10Imm: PatLeaf<(build_vector), [{
>> - return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0;
>> + return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).getNode() != 0;
>> }], v4i32Uns10Imm_xform>;
>>
>> // v4i32SExt16Imm_xform function: convert build_vector to 16-bit
>> sign extended
>> @@ -343,7 +343,7 @@
>> // v4i32SExt16Imm: Predicate test for 16-bit sign extended immediate
>> constant
>> // load, works in conjunction with its transform function.
>> def v4i32SExt16Imm: PatLeaf<(build_vector), [{
>> - return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32).Val != 0;
>> + return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32).getNode() != 0;
>> }], v4i32SExt16Imm_xform>;
>>
>> // v4i32Uns18Imm_xform function: convert build_vector to 18-bit
>> unsigned
>> @@ -355,7 +355,7 @@
>> // v4i32Uns18Imm: Predicate test for 18-bit unsigned immediate
>> constant load,
>> // works in conjunction with its transform function.
>> def v4i32Uns18Imm: PatLeaf<(build_vector), [{
>> - return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32).Val != 0;
>> + return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32).getNode() != 0;
>> }], v4i32Uns18Imm_xform>;
>>
>> // ILHUvec_get_imm xform function: convert build_vector to ILHUvec
>> imm constant
>> @@ -366,7 +366,7 @@
>>
>> /// immILHUvec: Predicate test for a ILHU constant vector.
>> def immILHUvec: PatLeaf<(build_vector), [{
>> - return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32).Val != 0;
>> + return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32).getNode() != 0;
>> }], ILHUvec_get_imm>;
>>
>> // Catch-all for any other i32 vector constants
>> @@ -375,7 +375,7 @@
>> }]>;
>>
>> def v4i32Imm: PatLeaf<(build_vector), [{
>> - return SPU::get_v4i32_imm(N, *CurDAG).Val != 0;
>> + return SPU::get_v4i32_imm(N, *CurDAG).getNode() != 0;
>> }], v4i32_get_imm>;
>>
>> // v2i64SExt10Imm_xform function: convert build_vector to 10-bit
>> sign extended
>> @@ -387,7 +387,7 @@
>> // v2i64SExt10Imm: Predicate test for 10-bit sign extended immediate
>> constant
>> // load, works in conjunction with its transform function.
>> def v2i64SExt10Imm: PatLeaf<(build_vector), [{
>> - return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64).Val != 0;
>> + return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64).getNode() != 0;
>> }], v2i64SExt10Imm_xform>;
>>
>> // v2i64SExt16Imm_xform function: convert build_vector to 16-bit
>> sign extended
>> @@ -399,7 +399,7 @@
>> // v2i64SExt16Imm: Predicate test for 16-bit sign extended immediate
>> constant
>> // load, works in conjunction with its transform function.
>> def v2i64SExt16Imm: PatLeaf<(build_vector), [{
>> - return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64).Val != 0;
>> + return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64).getNode() != 0;
>> }], v2i64SExt16Imm_xform>;
>>
>> // v2i64Uns18Imm_xform function: convert build_vector to 18-bit
>> unsigned
>> @@ -411,12 +411,12 @@
>> // v2i64Uns18Imm: Predicate test for 18-bit unsigned immediate
>> constant load,
>> // works in conjunction with its transform function.
>> def v2i64Uns18Imm: PatLeaf<(build_vector), [{
>> - return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64).Val != 0;
>> + return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64).getNode() != 0;
>> }], v2i64Uns18Imm_xform>;
>>
>> /// immILHUvec: Predicate test for a ILHU constant vector.
>> def immILHUvec_i64: PatLeaf<(build_vector), [{
>> - return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i64).Val != 0;
>> + return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i64).getNode() != 0;
>> }], ILHUvec_get_imm>;
>>
>> // Catch-all for any other i32 vector constants
>> @@ -425,7 +425,7 @@
>> }]>;
>>
>> def v2i64Imm: PatLeaf<(build_vector), [{
>> - return SPU::get_v2i64_imm(N, *CurDAG).Val != 0;
>> + return SPU::get_v2i64_imm(N, *CurDAG).getNode() != 0;
>> }], v2i64_get_imm>;
>>
>> //
>> =
>> =
>> =
>> ----------------------------------------------------------------------=
>> ==//
>>
>> Modified: llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp (original)
>> +++ llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -105,7 +105,7 @@
>> }
>>
>> SDNode *IA64DAGToDAGISel::SelectDIV(SDValue Op) {
>> - SDNode *N = Op.Val;
>> + SDNode *N = Op.getNode();
>> SDValue Chain = N->getOperand(0);
>> SDValue Tmp1 = N->getOperand(0);
>> SDValue Tmp2 = N->getOperand(1);
>> @@ -304,7 +304,7 @@
>> // Select - Convert the specified operand from a target-independent
>> to a
>> // target-specific node if it hasn't already been changed.
>> SDNode *IA64DAGToDAGISel::Select(SDValue Op) {
>> - SDNode *N = Op.Val;
>> + SDNode *N = Op.getNode();
>> if (N->isMachineOpcode())
>> return NULL; // Already selected.
>>
>> @@ -367,7 +367,7 @@
>> }
>>
>> // Finally, once everything is setup, emit the call itself
>> - if(InFlag.Val)
>> + if (InFlag.getNode())
>> Chain = SDValue(CurDAG->getTargetNode(CallOpcode, MVT::Other,
>> MVT::Flag,
>> CallOperand, InFlag), 0);
>> else // there might be no arguments
>>
>> Modified: llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -387,8 +387,8 @@
>> break;
>> }
>>
>> - if(ValToStore.Val) {
>> - if(!StackPtr.Val) {
>> + if(ValToStore.getNode()) {
>> + if(!StackPtr.getNode()) {
>> StackPtr = DAG.getRegister(IA64::r12, MVT::i64);
>> }
>> SDValue PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
>> @@ -397,7 +397,7 @@
>> ArgOffset += ObjSize;
>> }
>>
>> - if(ValToConvert.Val) {
>> + if(ValToConvert.getNode()) {
>> Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64,
>> ValToConvert));
>> }
>> }
>> @@ -471,7 +471,7 @@
>> CallOperands.push_back(Callee);
>>
>> // emit the call itself
>> - if (InFlag.Val)
>> + if (InFlag.getNode())
>> CallOperands.push_back(InFlag);
>> else
>> assert(0 && "this should never happen!\n");
>>
>> Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original)
>> +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -193,7 +193,7 @@
>> SDNode* MipsDAGToDAGISel::
>> Select(SDValue N)
>> {
>> - SDNode *Node = N.Val;
>> + SDNode *Node = N.getNode();
>> unsigned Opcode = Node->getOpcode();
>>
>> // Dump information about the Node being selected
>> @@ -252,7 +252,7 @@
>> SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, VT,
>> SDValue(Carry,0), RHS);
>>
>> - return CurDAG->SelectNodeTo(N.Val, MOp, VT, MVT::Flag,
>> + return CurDAG->SelectNodeTo(N.getNode(), MOp, VT, MVT::Flag,
>> LHS, SDValue(AddCarry,0));
>> }
>>
>> @@ -391,8 +391,8 @@
>>
>> #ifndef NDEBUG
>> DOUT << std::string(Indent-2, ' ') << "=> ";
>> - if (ResNode == NULL || ResNode == N.Val)
>> - DEBUG(N.Val->dump(CurDAG));
>> + if (ResNode == NULL || ResNode == N.getNode())
>> + DEBUG(N.getNode()->dump(CurDAG));
>> else
>> DEBUG(ResNode->dump(CurDAG));
>> DOUT << "\n";
>>
>> Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -602,7 +602,7 @@
>> MFI->CreateFixedObject(VTsize, (VTsize*3));
>> }
>>
>> - CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
>> + CCInfo.AnalyzeCallOperands(Op.getNode(), CC_Mips);
>>
>> // Get a count of how many bytes are to be pushed on the stack.
>> unsigned NumBytes = CCInfo.getNextStackOffset();
>> @@ -706,7 +706,7 @@
>> Ops.push_back(DAG.getRegister(RegsToPass[i].first,
>>
>> RegsToPass[i].second.getValueType()));
>>
>> - if (InFlag.Val)
>> + if (InFlag.getNode())
>> Ops.push_back(InFlag);
>>
>> Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0],
>> Ops.size());
>> @@ -750,7 +750,7 @@
>>
>> // Handle result values, copying them out of physregs into vregs
>> that we
>> // return.
>> - return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG),
>> Op.getResNo());
>> + return SDValue(LowerCallResult(Chain, InFlag, Op.getNode(), CC,
>> DAG), Op.getResNo());
>> }
>>
>> /// LowerCallResult - Lower the result values of an ISD::CALL into
>> the
>> @@ -783,7 +783,7 @@
>>
>> // Merge everything together with a MERGE_VALUES node.
>> return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
>> - ResultVals.size()).Val;
>> + ResultVals.size()).getNode();
>> }
>>
>> //
>> =
>> =
>> =
>> ----------------------------------------------------------------------=
>> ==//
>> @@ -814,7 +814,7 @@
>> SmallVector<CCValAssign, 16> ArgLocs;
>> CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
>>
>> - CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
>> + CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_Mips);
>> SmallVector<SDValue, 16> ArgValues;
>> SDValue StackPtr;
>>
>> @@ -865,7 +865,7 @@
>> // To meet ABI, when VARARGS are passed on registers, the
>> registers
>> // must have their values written to the caller stack frame.
>> if ((isVarArg) && (Subtarget->isABI_O32())) {
>> - if (StackPtr.Val == 0)
>> + if (StackPtr.getNode() == 0)
>> StackPtr = DAG.getRegister(StackReg, getPointerTy());
>>
>> // The stack pointer offset is relative to the caller stack
>> frame.
>> @@ -925,7 +925,7 @@
>> ArgValues.push_back(Root);
>>
>> // Return the new list of results.
>> - return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
>> + return DAG.getMergeValues(Op.getNode()->getVTList(),
>> &ArgValues[0],
>> ArgValues.size()).getValue(Op.getResNo());
>> }
>>
>> @@ -946,7 +946,7 @@
>> CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
>>
>> // Analize return values of ISD::RET
>> - CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
>> + CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Mips);
>>
>> // If this is the first return lowered for this function, add
>> // the regs to the liveout set for the function.
>> @@ -992,7 +992,7 @@
>> }
>>
>> // Return on Mips is always a "jr $ra"
>> - if (Flag.Val)
>> + if (Flag.getNode())
>> return DAG.getNode(MipsISD::Ret, MVT::Other,
>> Chain, DAG.getRegister(Mips::RA, MVT::i32),
>> Flag);
>> else // Return Void
>>
>> Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp (original)
>> +++ llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -168,11 +168,11 @@
>> if (LD) {
>> fsr = LD->getBasePtr();
>> }
>> - else if (isa<RegisterSDNode>(N.Val)) {
>> + else if (isa<RegisterSDNode>(N.getNode())) {
>> //FIXME an attempt to retrieve the register number
>> //but does not work
>> DOUT << "this is a register\n";
>> - Reg = dyn_cast<RegisterSDNode>(N.Val);
>> + Reg = dyn_cast<RegisterSDNode>(N.getNode());
>> fsr = CurDAG->getRegister(Reg->getReg(),MVT::i16);
>> }
>> else {
>> @@ -198,7 +198,7 @@
>> return true;
>> }
>> else if (N.getOpcode() == PIC16ISD::Package) {
>> - CurDAG->setGraphColor(Op.Val, "blue");
>> + CurDAG->setGraphColor(Op.getNode(), "blue");
>> CurDAG->viewGraph();
>> }
>>
>> @@ -227,7 +227,7 @@
>> /// expanded, promoted and normal instructions.
>> SDNode* PIC16DAGToDAGISel::Select(SDValue N)
>> {
>> - SDNode *Node = N.Val;
>> + SDNode *Node = N.getNode();
>> unsigned Opcode = Node->getOpcode();
>>
>> // Dump information about the Node being selected
>> @@ -262,8 +262,8 @@
>>
>> #ifndef NDEBUG
>> DOUT << std::string(Indent-2, ' ') << "=> ";
>> - if (ResNode == NULL || ResNode == N.Val)
>> - DEBUG(N.Val->dump(CurDAG));
>> + if (ResNode == NULL || ResNode == N.getNode())
>> + DEBUG(N.getNode()->dump(CurDAG));
>> else
>> DEBUG(ResNode->dump(CurDAG));
>> DOUT << "\n";
>>
>> Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -334,7 +334,7 @@
>> LoadSDNode *LD = cast<LoadSDNode>(N);
>> SDValue Ptr = LD->getBasePtr();
>> if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
>> - if (ISD::isNON_TRUNCStore(Chain.Val)) {
>> + if (ISD::isNON_TRUNCStore(Chain.getNode())) {
>> StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
>> if (PrevST->getBasePtr() == Ptr &&
>> PrevST->getValue().getValueType() == N->getValueType(0))
>> @@ -352,7 +352,7 @@
>> Outs[1] = DAG.getLoad(MVT::i8, Chain, toWorklist, NULL, 0);
>> // FIXME: Add to worklist may not be needed.
>> // It is meant to merge sequences of add with constant into one.
>> - DCI.AddToWorklist(toWorklist.Val);
>> + DCI.AddToWorklist(toWorklist.getNode());
>>
>> // Create the tokenfactors and carry it on to the build_pair node
>> OutChains[0] = Outs[0].getValue(1);
>> @@ -443,7 +443,7 @@
>> changed = true;
>> // LowerLOAD returns a Package node or it may combine and return
>> // anything else.
>> - SDValue lowered = LowerLOAD(InOp[i].Val, DAG, DCI);
>> + SDValue lowered = LowerLOAD(InOp[i].getNode(), DAG, DCI);
>>
>> // So If LowerLOAD returns something other than Package,
>> // then just call ADD again.
>> @@ -462,7 +462,7 @@
>> changed = true;
>> // Must call LowerADDSUB recursively here,
>> // LowerADDSUB returns a Package node.
>> - SDValue lowered = LowerADDSUB(InOp[i].Val, DAG, DCI);
>> + SDValue lowered = LowerADDSUB(InOp[i].getNode(), DAG, DCI);
>>
>> LoOps[i] = lowered.getOperand(0);
>> HiOps[i] = lowered.getOperand(1);
>> @@ -543,7 +543,7 @@
>> // FIXME: Just copy right now.
>> ArgValues.push_back(Root);
>>
>> - return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
>> + return DAG.getMergeValues(Op.getNode()->getVTList(),
>> &ArgValues[0],
>> ArgValues.size()).getValue(Op.getResNo());
>> }
>>
>> @@ -622,7 +622,7 @@
>> if ((Src.getOpcode() == ISD::ANY_EXTEND) ||
>> (Src.getOpcode() == ISD::SIGN_EXTEND) ||
>> (Src.getOpcode() == ISD::ZERO_EXTEND)) {
>> - Src = Src.Val->getOperand(0);
>> + Src = Src.getNode()->getOperand(0);
>> Stores[0] = DAG.getStore(Chain, Src, Dest, NULL,0);
>> return Stores[0];
>> }
>> @@ -721,10 +721,10 @@
>> // We want to merge sequence of add with constant to one
>> add and a
>> // constant, so add the ADD node to worklist to have llvm
>> do that
>> // automatically.
>> - DCI.AddToWorklist(toWorkList.Val);
>> + DCI.AddToWorklist(toWorkList.getNode());
>>
>> // We don't need the Package so add to worklist so llvm
>> deletes it
>> - DCI.AddToWorklist(Src.Val);
>> + DCI.AddToWorklist(Src.getNode());
>> retVal = DAG.getNode(ISD::TokenFactor, MVT::Other,
>> &Stores[0], 2);
>> }
>>
>>
>> Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
>> +++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -294,7 +294,7 @@
>> BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR8), GlobalBaseReg);
>> }
>> }
>> - return CurDAG->getRegister(GlobalBaseReg,
>> PPCLowering.getPointerTy()).Val;
>> + return CurDAG->getRegister(GlobalBaseReg,
>> PPCLowering.getPointerTy()).getNode();
>> }
>>
>> /// isIntS16Immediate - This method tests to see if the node is
>> either a 32-bit
>> @@ -313,7 +313,7 @@
>> }
>>
>> static bool isIntS16Immediate(SDValue Op, short &Imm) {
>> - return isIntS16Immediate(Op.Val, Imm);
>> + return isIntS16Immediate(Op.getNode(), Imm);
>> }
>>
>>
>> @@ -340,7 +340,7 @@
>> // isInt32Immediate - This method tests to see if a constant operand.
>> // If so Imm will receive the 32 bit value.
>> static bool isInt32Immediate(SDValue N, unsigned &Imm) {
>> - return isInt32Immediate(N.Val, Imm);
>> + return isInt32Immediate(N.getNode(), Imm);
>> }
>>
>>
>> @@ -348,7 +348,7 @@
>> // opcode and that it has a immediate integer right operand.
>> // If so Imm will receive the 32 bit value.
>> static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned&
>> Imm) {
>> - return N->getOpcode() == Opc && isInt32Immediate(N-
>>> getOperand(1).Val, Imm);
>> + return N->getOpcode() == Opc && isInt32Immediate(N-
>>> getOperand(1).getNode(), Imm);
>> }
>>
>> bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB,
>> unsigned &ME) {
>> @@ -384,7 +384,7 @@
>> unsigned Indeterminant = ~0; // bit mask marking indeterminant
>> results
>> unsigned Opcode = N->getOpcode();
>> if (N->getNumOperands() != 2 ||
>> - !isInt32Immediate(N->getOperand(1).Val, Shift) || (Shift >
>> 31))
>> + !isInt32Immediate(N->getOperand(1).getNode(), Shift) ||
>> (Shift > 31))
>> return false;
>>
>> if (Opcode == ISD::SHL) {
>> @@ -540,7 +540,7 @@
>> } else if (LHS.getValueType() == MVT::i64) {
>> uint64_t Imm;
>> if (CC == ISD::SETEQ || CC == ISD::SETNE) {
>> - if (isInt64Immediate(RHS.Val, Imm)) {
>> + if (isInt64Immediate(RHS.getNode(), Imm)) {
>> // SETEQ/SETNE comparison with 16-bit immediate, fold it.
>> if (isUInt16(Imm))
>> return SDValue(CurDAG->getTargetNode(PPC::CMPLDI,
>> MVT::i64, LHS,
>> @@ -568,7 +568,7 @@
>> }
>> Opc = PPC::CMPLD;
>> } else if (ISD::isUnsignedIntSetCC(CC)) {
>> - if (isInt64Immediate(RHS.Val, Imm) && isUInt16(Imm))
>> + if (isInt64Immediate(RHS.getNode(), Imm) && isUInt16(Imm))
>> return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64,
>> LHS,
>> getI64Imm(Imm &
>> 0xFFFF)), 0);
>> Opc = PPC::CMPLD;
>> @@ -653,7 +653,7 @@
>> }
>>
>> SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) {
>> - SDNode *N = Op.Val;
>> + SDNode *N = Op.getNode();
>> unsigned Imm;
>> ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
>> if (isInt32Immediate(N->getOperand(1), Imm)) {
>> @@ -773,7 +773,7 @@
>> // Select - Convert the specified operand from a target-independent
>> to a
>> // target-specific node if it hasn't already been changed.
>> SDNode *PPCDAGToDAGISel::Select(SDValue Op) {
>> - SDNode *N = Op.Val;
>> + SDNode *N = Op.getNode();
>> if (N->isMachineOpcode())
>> return NULL; // Already selected.
>>
>> @@ -974,7 +974,7 @@
>> // If this is an and of a value rotated between 0 and 31 bits
>> and then and'd
>> // with a mask, emit rlwinm
>> if (isInt32Immediate(N->getOperand(1), Imm) &&
>> - isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB,
>> ME)) {
>> + isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH,
>> MB, ME)) {
>> SDValue Val = N->getOperand(0).getOperand(0);
>> AddToISelQueue(Val);
>> SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB),
>> getI32Imm(ME) };
>> @@ -1025,7 +1025,7 @@
>> break;
>> case ISD::SHL: {
>> unsigned Imm, SH, MB, ME;
>> - if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm)
>> &&
>> + if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND,
>> Imm) &&
>> isRotateAndMask(N, Imm, true, SH, MB, ME)) {
>> AddToISelQueue(N->getOperand(0).getOperand(0));
>> SDValue Ops[] = { N->getOperand(0).getOperand(0),
>> @@ -1038,7 +1038,7 @@
>> }
>> case ISD::SRL: {
>> unsigned Imm, SH, MB, ME;
>> - if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm)
>> &&
>> + if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND,
>> Imm) &&
>> isRotateAndMask(N, Imm, true, SH, MB, ME)) {
>> AddToISelQueue(N->getOperand(0).getOperand(0));
>> SDValue Ops[] = { N->getOperand(0).getOperand(0),
>>
>> Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -423,7 +423,7 @@
>> static bool isFloatingPointZero(SDValue Op) {
>> if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
>> return CFP->getValueAPF().isZero();
>> - else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
>> + else if (ISD::isEXTLoad(Op.getNode()) ||
>> ISD::isNON_EXTLoad(Op.getNode())) {
>> // Maybe this has already been legalized into the constant pool?
>> if (ConstantPoolSDNode *CP =
>> dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
>> if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
>> @@ -625,7 +625,7 @@
>> if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
>>
>>
>> - if (UniquedVals[i&(Multiple-1)].Val == 0)
>> + if (UniquedVals[i&(Multiple-1)].getNode() == 0)
>> UniquedVals[i&(Multiple-1)] = N->getOperand(i);
>> else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
>> return SDValue(); // no match.
>> @@ -640,21 +640,21 @@
>> bool LeadingZero = true;
>> bool LeadingOnes = true;
>> for (unsigned i = 0; i != Multiple-1; ++i) {
>> - if (UniquedVals[i].Val == 0) continue; // Must have been
>> undefs.
>> + if (UniquedVals[i].getNode() == 0) continue; // Must have
>> been undefs.
>>
>> LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])-
>>> isNullValue();
>> LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])-
>>> isAllOnesValue();
>> }
>> // Finally, check the least significant entry.
>> if (LeadingZero) {
>> - if (UniquedVals[Multiple-1].Val == 0)
>> + if (UniquedVals[Multiple-1].getNode() == 0)
>> return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
>> int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])-
>>> getValue();
>> if (Val < 16)
>> return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 ->
>> vspltisw(4)
>> }
>> if (LeadingOnes) {
>> - if (UniquedVals[Multiple-1].Val == 0)
>> + if (UniquedVals[Multiple-1].getNode() == 0)
>> return DAG.getTargetConstant(~0U, MVT::i32); //
>> -1,-1,-1,undef
>> int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])-
>>> getSignExtended();
>> if (Val >= -16) // -1,-1,-1,-2 ->
>> vspltisw(-2)
>> @@ -667,13 +667,13 @@
>> // Check to see if this buildvec has a single non-undef value in
>> its elements.
>> for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
>> if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
>> - if (OpVal.Val == 0)
>> + if (OpVal.getNode() == 0)
>> OpVal = N->getOperand(i);
>> else if (OpVal != N->getOperand(i))
>> return SDValue();
>> }
>>
>> - if (OpVal.Val == 0) return SDValue(); // All UNDEF: use implicit
>> def.
>> + if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use
>> implicit def.
>>
>> unsigned ValSizeInBytes = 0;
>> uint64_t Value = 0;
>> @@ -735,7 +735,7 @@
>> return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
>> }
>> static bool isIntS16Immediate(SDValue Op, short &Imm) {
>> - return isIntS16Immediate(Op.Val, Imm);
>> + return isIntS16Immediate(Op.getNode(), Imm);
>> }
>>
>>
>> @@ -1389,7 +1389,7 @@
>> // to handle Elf here.
>> unsigned VecArgOffset = ArgOffset;
>> if (!isVarArg && !isPPC64) {
>> - for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo !=
>> e;
>> + for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1;
>> ArgNo != e;
>> ++ArgNo) {
>> MVT ObjectVT = Op.getValue(ArgNo).getValueType();
>> unsigned ObjSize = ObjectVT.getSizeInBits()/8;
>> @@ -1439,7 +1439,7 @@
>>
>> SmallVector<SDValue, 8> MemOps;
>> unsigned nAltivecParamsAtEnd = 0;
>> - for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo !=
>> e; ++ArgNo) {
>> + for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1;
>> ArgNo != e; ++ArgNo) {
>> SDValue ArgVal;
>> bool needsLoad = false;
>> MVT ObjectVT = Op.getValue(ArgNo).getValueType();
>> @@ -1765,7 +1765,7 @@
>> ArgValues.push_back(Root);
>>
>> // Return the new list of results.
>> - return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
>> + return DAG.getMergeValues(Op.getNode()->getVTList(),
>> &ArgValues[0],
>> ArgValues.size());
>> }
>>
>> @@ -1906,7 +1906,7 @@
>> return 0; // Top 6 bits have to be sext of immediate.
>>
>> return DAG.getConstant((int)C->getValue() >> 2,
>> -
>> DAG.getTargetLoweringInfo().getPointerTy()).Val;
>> +
>> DAG.getTargetLoweringInfo().getPointerTy()).getNode();
>> }
>>
>> namespace {
>> @@ -2001,10 +2001,10 @@
>> MVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
>> LROpOut = getReturnAddrFrameIndex(DAG);
>> LROpOut = DAG.getLoad(VT, Chain, LROpOut, NULL, 0);
>> - Chain = SDValue(LROpOut.Val, 1);
>> + Chain = SDValue(LROpOut.getNode(), 1);
>> FPOpOut = getFramePointerFrameIndex(DAG);
>> FPOpOut = DAG.getLoad(VT, Chain, FPOpOut, NULL, 0);
>> - Chain = SDValue(FPOpOut.Val, 1);
>> + Chain = SDValue(FPOpOut.getNode(), 1);
>> }
>> return Chain;
>> }
>> @@ -2193,12 +2193,12 @@
>> SDValue Const = DAG.getConstant(4 - Size,
>> PtrOff.getValueType());
>> SDValue AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff,
>> Const);
>> SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
>> - CallSeqStart.Val->getOperand(0),
>> + CallSeqStart.getNode()-
>>> getOperand(0),
>> Flags, DAG, Size);
>> // This must go outside the CALLSEQ_START..END.
>> SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
>> - CallSeqStart.Val->getOperand(1));
>> - DAG.ReplaceAllUsesWith(CallSeqStart.Val,
>> NewCallSeqStart.Val);
>> + CallSeqStart.getNode()-
>>> getOperand(1));
>> + DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
>> NewCallSeqStart.getNode());
>> Chain = CallSeqStart = NewCallSeqStart;
>> ArgOffset += PtrByteSize;
>> }
>> @@ -2208,12 +2208,12 @@
>> // code assumes it is there, even if it could be put entirely
>> into
>> // registers. (This is not what the doc says.)
>> SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
>> - CallSeqStart.Val->getOperand(0),
>> + CallSeqStart.getNode()->getOperand(0),
>> Flags, DAG, Size);
>> // This must go outside the CALLSEQ_START..END.
>> SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
>> - CallSeqStart.Val->getOperand(1));
>> - DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val);
>> + CallSeqStart.getNode()->getOperand(1));
>> + DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
>> NewCallSeqStart.getNode());
>> Chain = CallSeqStart = NewCallSeqStart;
>> // And copy the pieces of it that fit into registers.
>> for (unsigned j=0; j<Size; j+=PtrByteSize) {
>> @@ -2432,7 +2432,7 @@
>> CallSeqOps.push_back(Chain);
>> CallSeqOps.push_back(DAG.getIntPtrConstant(NumBytes));
>> CallSeqOps.push_back(DAG.getIntPtrConstant(0));
>> - if (InFlag.Val)
>> + if (InFlag.getNode())
>> CallSeqOps.push_back(InFlag);
>> Chain = DAG.getNode(ISD::CALLSEQ_END, CallSeqNodeTys,
>> &CallSeqOps[0],
>> CallSeqOps.size());
>> @@ -2460,7 +2460,7 @@
>> // Otherwise, this is an indirect call. We have to use a MTCTR/
>> BCTRL pair
>> // to do the call, we can't use PPCISD::CALL.
>> SDValue MTCTROps[] = {Chain, Callee, InFlag};
>> - Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+
>> (InFlag.Val!=0));
>> + Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+
>> (InFlag.getNode()!=0));
>> InFlag = Chain.getValue(1);
>>
>> // Copy the callee address into R12/X12 on darwin.
>> @@ -2475,14 +2475,14 @@
>> NodeTys.push_back(MVT::Flag);
>> Ops.push_back(Chain);
>> CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF;
>> - Callee.Val = 0;
>> + Callee.setNode(0);
>> // Add CTR register as callee so a bctr can be emitted later.
>> if (isTailCall)
>> Ops.push_back(DAG.getRegister(PPC::CTR, getPointerTy()));
>> }
>>
>> // If this is a direct call, pass the chain and the callee.
>> - if (Callee.Val) {
>> + if (Callee.getNode()) {
>> Ops.push_back(Chain);
>> Ops.push_back(Callee);
>> }
>> @@ -2502,16 +2502,16 @@
>> int BytesCalleePops =
>> (CC==CallingConv::Fast && PerformTailCallOpt) ? NumBytes : 0;
>>
>> - if (InFlag.Val)
>> + if (InFlag.getNode())
>> Ops.push_back(InFlag);
>>
>> // Emit tail call.
>> if (isTailCall) {
>> - assert(InFlag.Val &&
>> + assert(InFlag.getNode() &&
>> "Flag must be set. Depend on flag being set in LowerRET");
>> Chain = DAG.getNode(PPCISD::TAILCALL,
>> - Op.Val->getVTList(), &Ops[0], Ops.size());
>> - return SDValue(Chain.Val, Op.getResNo());
>> + Op.getNode()->getVTList(), &Ops[0],
>> Ops.size());
>> + return SDValue(Chain.getNode(), Op.getResNo());
>> }
>>
>> Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
>> @@ -2521,14 +2521,14 @@
>> DAG.getConstant(NumBytes, PtrVT),
>> DAG.getConstant(BytesCalleePops, PtrVT),
>> InFlag);
>> - if (Op.Val->getValueType(0) != MVT::Other)
>> + if (Op.getNode()->getValueType(0) != MVT::Other)
>> InFlag = Chain.getValue(1);
>>
>> SmallVector<SDValue, 16> ResultVals;
>> SmallVector<CCValAssign, 16> RVLocs;
>> unsigned CallerCC = DAG.getMachineFunction().getFunction()-
>>> getCallingConv();
>> CCState CCInfo(CallerCC, isVarArg, TM, RVLocs);
>> - CCInfo.AnalyzeCallResult(Op.Val, RetCC_PPC);
>> + CCInfo.AnalyzeCallResult(Op.getNode(), RetCC_PPC);
>>
>> // Copy all of the result registers out of their specified physreg.
>> for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
>> @@ -2546,7 +2546,7 @@
>>
>> // Otherwise, merge everything together with a MERGE_VALUES node.
>> ResultVals.push_back(Chain);
>> - SDValue Res = DAG.getMergeValues(Op.Val->getVTList(),
>> &ResultVals[0],
>> + SDValue Res = DAG.getMergeValues(Op.getNode()->getVTList(),
>> &ResultVals[0],
>> ResultVals.size());
>> return Res.getValue(Op.getResNo());
>> }
>> @@ -2557,7 +2557,7 @@
>> unsigned CC = DAG.getMachineFunction().getFunction()-
>>> getCallingConv();
>> bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
>> CCState CCInfo(CC, isVarArg, TM, RVLocs);
>> - CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC);
>> + CCInfo.AnalyzeReturn(Op.getNode(), RetCC_PPC);
>>
>> // If this is the first return lowered for this function, add the
>> regs to the
>> // liveout set for the function.
>> @@ -2607,7 +2607,7 @@
>> Flag = Chain.getValue(1);
>> }
>>
>> - if (Flag.Val)
>> + if (Flag.getNode())
>> return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag);
>> else
>> return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain);
>> @@ -2818,11 +2818,11 @@
>> SDValue PPCTargetLowering::LowerFP_ROUND_INREG(SDValue Op,
>> SelectionDAG &DAG) {
>> assert(Op.getValueType() == MVT::ppcf128);
>> - SDNode *Node = Op.Val;
>> + SDNode *Node = Op.getNode();
>> assert(Node->getOperand(0).getValueType() == MVT::ppcf128);
>> - assert(Node->getOperand(0).Val->getOpcode() == ISD::BUILD_PAIR);
>> - SDValue Lo = Node->getOperand(0).Val->getOperand(0);
>> - SDValue Hi = Node->getOperand(0).Val->getOperand(1);
>> + assert(Node->getOperand(0).getNode()->getOpcode() ==
>> ISD::BUILD_PAIR);
>> + SDValue Lo = Node->getOperand(0).getNode()->getOperand(0);
>> + SDValue Hi = Node->getOperand(0).getNode()->getOperand(1);
>>
>> // This sequence changes FPSCR to do round-to-zero, adds the two
>> halves
>> // of the long double, and puts FPSCR back the way it was. We do
>> not
>> @@ -3237,7 +3237,7 @@
>> // zero.
>> uint64_t VectorBits[2];
>> uint64_t UndefBits[2];
>> - if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
>> + if (GetConstantBuildVectorBits(Op.getNode(), VectorBits,
>> UndefBits))
>> return SDValue(); // Not a constant vector.
>>
>> // If this is a splat (repetition) of a value across the whole
>> vector, return
>> @@ -3483,18 +3483,18 @@
>> // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they
>> can be
>> // selected by the instruction selector.
>> if (V2.getOpcode() == ISD::UNDEF) {
>> - if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
>> - PPC::isSplatShuffleMask(PermMask.Val, 2) ||
>> - PPC::isSplatShuffleMask(PermMask.Val, 4) ||
>> - PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
>> - PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
>> - PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
>> - PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
>> - PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
>> - PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
>> - PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
>> - PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
>> - PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
>> + if (PPC::isSplatShuffleMask(PermMask.getNode(), 1) ||
>> + PPC::isSplatShuffleMask(PermMask.getNode(), 2) ||
>> + PPC::isSplatShuffleMask(PermMask.getNode(), 4) ||
>> + PPC::isVPKUWUMShuffleMask(PermMask.getNode(), true) ||
>> + PPC::isVPKUHUMShuffleMask(PermMask.getNode(), true) ||
>> + PPC::isVSLDOIShuffleMask(PermMask.getNode(), true) != -1 ||
>> + PPC::isVMRGLShuffleMask(PermMask.getNode(), 1, true) ||
>> + PPC::isVMRGLShuffleMask(PermMask.getNode(), 2, true) ||
>> + PPC::isVMRGLShuffleMask(PermMask.getNode(), 4, true) ||
>> + PPC::isVMRGHShuffleMask(PermMask.getNode(), 1, true) ||
>> + PPC::isVMRGHShuffleMask(PermMask.getNode(), 2, true) ||
>> + PPC::isVMRGHShuffleMask(PermMask.getNode(), 4, true)) {
>> return Op;
>> }
>> }
>> @@ -3502,15 +3502,15 @@
>> // Altivec has a variety of "shuffle immediates" that take two
>> vector inputs
>> // and produce a fixed permutation. If any of these match, do not
>> lower to
>> // VPERM.
>> - if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
>> - PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
>> - PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
>> - PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
>> - PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
>> - PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
>> - PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
>> - PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
>> - PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
>> + if (PPC::isVPKUWUMShuffleMask(PermMask.getNode(), false) ||
>> + PPC::isVPKUHUMShuffleMask(PermMask.getNode(), false) ||
>> + PPC::isVSLDOIShuffleMask(PermMask.getNode(), false) != -1 ||
>> + PPC::isVMRGLShuffleMask(PermMask.getNode(), 1, false) ||
>> + PPC::isVMRGLShuffleMask(PermMask.getNode(), 2, false) ||
>> + PPC::isVMRGLShuffleMask(PermMask.getNode(), 4, false) ||
>> + PPC::isVMRGHShuffleMask(PermMask.getNode(), 1, false) ||
>> + PPC::isVMRGHShuffleMask(PermMask.getNode(), 2, false) ||
>> + PPC::isVMRGHShuffleMask(PermMask.getNode(), 4, false))
>> return Op;
>>
>> // Check to see if this is a shuffle of 4-byte values. If so, we
>> can use our
>> @@ -3842,7 +3842,7 @@
>> // Use MERGE_VALUES to drop the chain result value and get a
>> node with one
>> // result. This requires turning off getMergeValues
>> simplification, since
>> // otherwise it will give us Res back.
>> - return DAG.getMergeValues(&Res, 1, false).Val;
>> + return DAG.getMergeValues(&Res, 1, false).getNode();
>> }
>> }
>> }
>> @@ -4292,17 +4292,17 @@
>> SDValue Val = N->getOperand(0).getOperand(0);
>> if (Val.getValueType() == MVT::f32) {
>> Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
>> - DCI.AddToWorklist(Val.Val);
>> + DCI.AddToWorklist(Val.getNode());
>> }
>>
>> Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
>> - DCI.AddToWorklist(Val.Val);
>> + DCI.AddToWorklist(Val.getNode());
>> Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
>> - DCI.AddToWorklist(Val.Val);
>> + DCI.AddToWorklist(Val.getNode());
>> if (N->getValueType(0) == MVT::f32) {
>> Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val,
>> DAG.getIntPtrConstant(0));
>> - DCI.AddToWorklist(Val.Val);
>> + DCI.AddToWorklist(Val.getNode());
>> }
>> return Val;
>> } else if (N->getOperand(0).getValueType() == MVT::i32) {
>> @@ -4322,20 +4322,20 @@
>> SDValue Val = N->getOperand(1).getOperand(0);
>> if (Val.getValueType() == MVT::f32) {
>> Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
>> - DCI.AddToWorklist(Val.Val);
>> + DCI.AddToWorklist(Val.getNode());
>> }
>> Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
>> - DCI.AddToWorklist(Val.Val);
>> + DCI.AddToWorklist(Val.getNode());
>>
>> Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N-
>>> getOperand(0), Val,
>> N->getOperand(2), N->getOperand(3));
>> - DCI.AddToWorklist(Val.Val);
>> + DCI.AddToWorklist(Val.getNode());
>> return Val;
>> }
>>
>> // Turn STORE (BSWAP) -> sthbrx/stwbrx.
>> if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
>> - N->getOperand(1).Val->hasOneUse() &&
>> + N->getOperand(1).getNode()->hasOneUse() &&
>> (N->getOperand(1).getValueType() == MVT::i32 ||
>> N->getOperand(1).getValueType() == MVT::i16)) {
>> SDValue BSwapOp = N->getOperand(1).getOperand(0);
>> @@ -4350,7 +4350,7 @@
>> break;
>> case ISD::BSWAP:
>> // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
>> - if (ISD::isNON_EXTLoad(N->getOperand(0).Val) &&
>> + if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
>> N->getOperand(0).hasOneUse() &&
>> (N->getValueType(0) == MVT::i32 || N->getValueType(0) ==
>> MVT::i16)) {
>> SDValue Load = N->getOperand(0);
>> @@ -4379,7 +4379,7 @@
>>
>> // Next, combine the load away, we give it a bogus result
>> value but a real
>> // chain result. The result value is dead because the bswap
>> is dead.
>> - DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1));
>> + DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
>>
>> // Return N so it doesn't get rechecked!
>> return SDValue(N, 0);
>> @@ -4398,7 +4398,7 @@
>> // Scan all of the users of the LHS, looking for VCMPo's that
>> match.
>> SDNode *VCMPoNode = 0;
>>
>> - SDNode *LHSN = N->getOperand(0).Val;
>> + SDNode *LHSN = N->getOperand(0).getNode();
>> for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN-
>>> use_end();
>> UI != E; ++UI)
>> if (UI->getOpcode() == PPCISD::VCMPo &&
>> @@ -4650,7 +4650,7 @@
>> }
>> }
>>
>> - if (Result.Val) {
>> + if (Result.getNode()) {
>> Ops.push_back(Result);
>> return;
>> }
>>
>> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td (original)
>> +++ llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td Thu Aug 28
>> 16:40:38 2008
>> @@ -113,7 +113,7 @@
>> return PPC::get_VSPLTI_elt(N, 1, *CurDAG);
>> }]>;
>> def vecspltisb : PatLeaf<(build_vector), [{
>> - return PPC::get_VSPLTI_elt(N, 1, *CurDAG).Val != 0;
>> + return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0;
>> }], VSPLTISB_get_imm>;
>>
>> // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH
>> imm.
>> @@ -121,7 +121,7 @@
>> return PPC::get_VSPLTI_elt(N, 2, *CurDAG);
>> }]>;
>> def vecspltish : PatLeaf<(build_vector), [{
>> - return PPC::get_VSPLTI_elt(N, 2, *CurDAG).Val != 0;
>> + return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0;
>> }], VSPLTISH_get_imm>;
>>
>> // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW
>> imm.
>> @@ -129,7 +129,7 @@
>> return PPC::get_VSPLTI_elt(N, 4, *CurDAG);
>> }]>;
>> def vecspltisw : PatLeaf<(build_vector), [{
>> - return PPC::get_VSPLTI_elt(N, 4, *CurDAG).Val != 0;
>> + return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0;
>> }], VSPLTISW_get_imm>;
>>
>> def V_immneg0 : PatLeaf<(build_vector), [{
>>
>> Modified: llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp (original)
>> +++ llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -120,7 +120,7 @@
>>
>> if (Addr.getOpcode() == ISD::ADD) {
>> if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
>> - Predicate_simm13(Addr.getOperand(1).Val))
>> + Predicate_simm13(Addr.getOperand(1).getNode()))
>> return false; // Let the reg+imm pattern catch this!
>> if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
>> Addr.getOperand(1).getOpcode() == SPISD::Lo)
>> @@ -136,7 +136,7 @@
>> }
>>
>> SDNode *SparcDAGToDAGISel::Select(SDValue Op) {
>> - SDNode *N = Op.Val;
>> + SDNode *N = Op.getNode();
>> if (N->isMachineOpcode())
>> return NULL; // Already selected.
>>
>>
>> Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -40,7 +40,7 @@
>> CCState CCInfo(CC, isVarArg, DAG.getTarget(), RVLocs);
>>
>> // Analize return values of ISD::RET
>> - CCInfo.AnalyzeReturn(Op.Val, RetCC_Sparc32);
>> + CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Sparc32);
>>
>> // If this is the first return lowered for this function, add the
>> regs to the
>> // liveout set for the function.
>> @@ -66,7 +66,7 @@
>> Flag = Chain.getValue(1);
>> }
>>
>> - if (Flag.Val)
>> + if (Flag.getNode())
>> return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain, Flag);
>> return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain);
>> }
>> @@ -233,7 +233,7 @@
>> // Analyze operands of the call, assigning locations to each
>> operand.
>> SmallVector<CCValAssign, 16> ArgLocs;
>> CCState CCInfo(CallingConv, isVarArg, DAG.getTarget(), ArgLocs);
>> - CCInfo.AnalyzeCallOperands(Op.Val, CC_Sparc32);
>> + CCInfo.AnalyzeCallOperands(Op.getNode(), CC_Sparc32);
>>
>> // Get the size of the outgoing arguments stack space requirement.
>> unsigned ArgsSize = CCInfo.getNextStackOffset();
>> @@ -374,7 +374,7 @@
>> break;
>> }
>>
>> - if (ValToStore.Val) {
>> + if (ValToStore.getNode()) {
>> SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
>> SDValue PtrOff = DAG.getConstant(ArgOffset, MVT::i32);
>> PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
>> @@ -416,7 +416,7 @@
>> NodeTys.push_back(MVT::Other); // Returns a chain
>> NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy
>> to use.
>> SDValue Ops[] = { Chain, Callee, InFlag };
>> - Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 :
>> 2);
>> + Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.getNode() ?
>> 3 : 2);
>> InFlag = Chain.getValue(1);
>>
>> Chain = DAG.getCALLSEQ_END(Chain,
>> @@ -428,7 +428,7 @@
>> SmallVector<CCValAssign, 16> RVLocs;
>> CCState RVInfo(CallingConv, isVarArg, DAG.getTarget(), RVLocs);
>>
>> - RVInfo.AnalyzeCallResult(Op.Val, RetCC_Sparc32);
>> + RVInfo.AnalyzeCallResult(Op.getNode(), RetCC_Sparc32);
>> SmallVector<SDValue, 8> ResultVals;
>>
>> // Copy all of the result registers out of their specified physreg.
>> @@ -448,7 +448,7 @@
>> ResultVals.push_back(Chain);
>>
>> // Merge everything together with a MERGE_VALUES node.
>> - return DAG.getMergeValues(Op.Val->getVTList(), &ResultVals[0],
>> + return DAG.getMergeValues(Op.getNode()->getVTList(),
>> &ResultVals[0],
>> ResultVals.size());
>> }
>>
>> @@ -803,7 +803,7 @@
>> }
>>
>> static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
>> - SDNode *Node = Op.Val;
>> + SDNode *Node = Op.getNode();
>> MVT VT = Node->getValueType(0);
>> SDValue InChain = Node->getOperand(0);
>> SDValue VAListPtr = Node->getOperand(1);
>>
>> Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -80,11 +80,11 @@
>> }
>> void dump() {
>> cerr << "X86ISelAddressMode " << this << "\n";
>> - cerr << "Base.Reg "; if (Base.Reg.Val!=0) Base.Reg.Val-
>> >dump();
>> + cerr << "Base.Reg "; if (Base.Reg.getNode()!=0)
>> Base.Reg.getNode()->dump();
>> else cerr << "nul";
>> cerr << " Base.FrameIndex " << Base.FrameIndex << "\n";
>> cerr << "isRIPRel " << isRIPRel << " Scale" << Scale << "\n";
>> - cerr << "IndexReg "; if (IndexReg.Val!=0) IndexReg.Val-
>> >dump();
>> + cerr << "IndexReg "; if (IndexReg.getNode()!=0)
>> IndexReg.getNode()->dump();
>> else cerr << "nul";
>> cerr << " Disp " << Disp << "\n";
>> cerr << "GV "; if (GV) GV->dump();
>> @@ -253,7 +253,7 @@
>> SDNode *User = *I;
>> for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
>> SDValue Op = User->getOperand(i);
>> - if (Op.Val == N && Op.getResNo() == FlagResNo)
>> + if (Op.getNode() == N && Op.getResNo() == FlagResNo)
>> return User;
>> }
>> }
>> @@ -272,7 +272,7 @@
>> return;
>>
>> for (unsigned i = 0, e = Use->getNumOperands(); !found && i != e; +
>> +i) {
>> - SDNode *N = Use->getOperand(i).Val;
>> + SDNode *N = Use->getOperand(i).getNode();
>> if (N == Skip)
>> continue;
>> if (N == Def) {
>> @@ -374,8 +374,8 @@
>> static void MoveBelowTokenFactor(SelectionDAG *CurDAG, SDValue Load,
>> SDValue Store, SDValue TF) {
>> SmallVector<SDValue, 4> Ops;
>> - for (unsigned i = 0, e = TF.Val->getNumOperands(); i != e; ++i)
>> - if (Load.Val == TF.getOperand(i).Val)
>> + for (unsigned i = 0, e = TF.getNode()->getNumOperands(); i != e; +
>> +i)
>> + if (Load.getNode() == TF.getOperand(i).getNode())
>> Ops.push_back(Load.getOperand(0));
>> else
>> Ops.push_back(TF.getOperand(i));
>> @@ -404,7 +404,7 @@
>>
>> if (N.hasOneUse() &&
>> N.getOperand(1) == Address &&
>> - N.Val->isOperandOf(Chain.Val)) {
>> + N.getNode()->isOperandOf(Chain.getNode())) {
>> Load = N;
>> return true;
>> }
>> @@ -416,8 +416,8 @@
>> static void MoveBelowCallSeqStart(SelectionDAG *CurDAG, SDValue Load,
>> SDValue Call, SDValue Chain) {
>> SmallVector<SDValue, 8> Ops;
>> - for (unsigned i = 0, e = Chain.Val->getNumOperands(); i != e; ++i)
>> - if (Load.Val == Chain.getOperand(i).Val)
>> + for (unsigned i = 0, e = Chain.getNode()->getNumOperands(); i !=
>> e; ++i)
>> + if (Load.getNode() == Chain.getOperand(i).getNode())
>> Ops.push_back(Load.getOperand(0));
>> else
>> Ops.push_back(Chain.getOperand(i));
>> @@ -425,8 +425,8 @@
>> CurDAG->UpdateNodeOperands(Load, Call.getOperand(0),
>> Load.getOperand(1), Load.getOperand(2));
>> Ops.clear();
>> - Ops.push_back(SDValue(Load.Val, 1));
>> - for (unsigned i = 1, e = Call.Val->getNumOperands(); i != e; ++i)
>> + Ops.push_back(SDValue(Load.getNode(), 1));
>> + for (unsigned i = 1, e = Call.getNode()->getNumOperands(); i !=
>> e; ++i)
>> Ops.push_back(Call.getOperand(i));
>> CurDAG->UpdateNodeOperands(Call, &Ops[0], Ops.size());
>> }
>> @@ -435,9 +435,9 @@
>> /// moved below CALLSEQ_START and the chains leading up to the call.
>> /// Return the CALLSEQ_START by reference as a second output.
>> static bool isCalleeLoad(SDValue Callee, SDValue &Chain) {
>> - if (Callee.Val == Chain.Val || !Callee.hasOneUse())
>> + if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
>> return false;
>> - LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.Val);
>> + LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
>> if (!LD ||
>> LD->isVolatile() ||
>> LD->getAddressingMode() != ISD::UNINDEXED ||
>> @@ -450,7 +450,7 @@
>> return false;
>> Chain = Chain.getOperand(0);
>> }
>> - return Chain.getOperand(0).Val == Callee.Val;
>> + return Chain.getOperand(0).getNode() == Callee.getNode();
>> }
>>
>>
>> @@ -530,7 +530,7 @@
>> continue;
>> SDValue Chain = I->getOperand(0);
>>
>> - if (Chain.Val->getOpcode() != ISD::TokenFactor)
>> + if (Chain.getNode()->getOpcode() != ISD::TokenFactor)
>> continue;
>>
>> SDValue N1 = I->getOperand(1);
>> @@ -542,7 +542,7 @@
>>
>> bool RModW = false;
>> SDValue Load;
>> - unsigned Opcode = N1.Val->getOpcode();
>> + unsigned Opcode = N1.getNode()->getOpcode();
>> switch (Opcode) {
>> case ISD::ADD:
>> case ISD::MUL:
>> @@ -786,7 +786,7 @@
>> return true;
>> }
>>
>> - int id = N.Val->getNodeId();
>> + int id = N.getNode()->getNodeId();
>> bool AlreadySelected = isSelected(id); // Already selected, not
>> yet replaced.
>>
>> switch (N.getOpcode()) {
>> @@ -808,14 +808,14 @@
>> // Under X86-64 non-small code model, GV (and friends) are 64-
>> bits.
>> // Also, base and index reg must be 0 in order to use rip as base.
>> if (is64Bit && (TM.getCodeModel() != CodeModel::Small ||
>> - AM.Base.Reg.Val || AM.IndexReg.Val))
>> + AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
>> break;
>> if (AM.GV != 0 || AM.CP != 0 || AM.ES != 0 || AM.JT != -1)
>> break;
>> // If value is available in a register both base and index
>> components have
>> // been picked, we can't fit the result available in the
>> register in the
>> // addressing mode. Duplicate GlobalAddress or ConstantPool as
>> displacement.
>> - if (!AlreadySelected || (AM.Base.Reg.Val && AM.IndexReg.Val)) {
>> + if (!AlreadySelected || (AM.Base.Reg.getNode() &&
>> AM.IndexReg.getNode())) {
>> SDValue N0 = N.getOperand(0);
>> if (GlobalAddressSDNode *G =
>> dyn_cast<GlobalAddressSDNode>(N0)) {
>> GlobalValue *GV = G->getGlobal();
>> @@ -847,7 +847,7 @@
>> }
>>
>> case ISD::FrameIndex:
>> - if (AM.BaseType == X86ISelAddressMode::RegBase &&
>> AM.Base.Reg.Val == 0) {
>> + if (AM.BaseType == X86ISelAddressMode::RegBase &&
>> AM.Base.Reg.getNode() == 0) {
>> AM.BaseType = X86ISelAddressMode::FrameIndexBase;
>> AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
>> return false;
>> @@ -855,23 +855,23 @@
>> break;
>>
>> case ISD::SHL:
>> - if (AlreadySelected || AM.IndexReg.Val != 0 || AM.Scale != 1 ||
>> AM.isRIPRel)
>> + if (AlreadySelected || AM.IndexReg.getNode() != 0 || AM.Scale !
>> = 1 || AM.isRIPRel)
>> break;
>>
>> - if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val-
>>> getOperand(1))) {
>> + if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getNode()-
>>> getOperand(1))) {
>> unsigned Val = CN->getValue();
>> if (Val == 1 || Val == 2 || Val == 3) {
>> AM.Scale = 1 << Val;
>> - SDValue ShVal = N.Val->getOperand(0);
>> + SDValue ShVal = N.getNode()->getOperand(0);
>>
>> // Okay, we know that we have a scale by now. However, if
>> the scaled
>> // value is an add of something and a constant, we can fold
>> the
>> // constant into the disp field here.
>> - if (ShVal.Val->getOpcode() == ISD::ADD && ShVal.hasOneUse()
>> &&
>> - isa<ConstantSDNode>(ShVal.Val->getOperand(1))) {
>> - AM.IndexReg = ShVal.Val->getOperand(0);
>> + if (ShVal.getNode()->getOpcode() == ISD::ADD &&
>> ShVal.hasOneUse() &&
>> + isa<ConstantSDNode>(ShVal.getNode()->getOperand(1))) {
>> + AM.IndexReg = ShVal.getNode()->getOperand(0);
>> ConstantSDNode *AddVal =
>> - cast<ConstantSDNode>(ShVal.Val->getOperand(1));
>> + cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
>> uint64_t Disp = AM.Disp + (AddVal->getValue() << Val);
>> if (isInt32(Disp))
>> AM.Disp = Disp;
>> @@ -894,31 +894,31 @@
>> // X*[3,5,9] -> X+X*[2,4,8]
>> if (!AlreadySelected &&
>> AM.BaseType == X86ISelAddressMode::RegBase &&
>> - AM.Base.Reg.Val == 0 &&
>> - AM.IndexReg.Val == 0 &&
>> + AM.Base.Reg.getNode() == 0 &&
>> + AM.IndexReg.getNode() == 0 &&
>> !AM.isRIPRel) {
>> - if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val-
>>> getOperand(1)))
>> + if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getNode()-
>>> getOperand(1)))
>> if (CN->getValue() == 3 || CN->getValue() == 5 || CN-
>>> getValue() == 9) {
>> AM.Scale = unsigned(CN->getValue())-1;
>>
>> - SDValue MulVal = N.Val->getOperand(0);
>> + SDValue MulVal = N.getNode()->getOperand(0);
>> SDValue Reg;
>>
>> // Okay, we know that we have a scale by now. However, if
>> the scaled
>> // value is an add of something and a constant, we can
>> fold the
>> // constant into the disp field here.
>> - if (MulVal.Val->getOpcode() == ISD::ADD &&
>> MulVal.hasOneUse() &&
>> - isa<ConstantSDNode>(MulVal.Val->getOperand(1))) {
>> - Reg = MulVal.Val->getOperand(0);
>> + if (MulVal.getNode()->getOpcode() == ISD::ADD &&
>> MulVal.hasOneUse() &&
>> + isa<ConstantSDNode>(MulVal.getNode()-
>> >getOperand(1))) {
>> + Reg = MulVal.getNode()->getOperand(0);
>> ConstantSDNode *AddVal =
>> - cast<ConstantSDNode>(MulVal.Val->getOperand(1));
>> + cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
>> uint64_t Disp = AM.Disp + AddVal->getValue() * CN-
>>> getValue();
>> if (isInt32(Disp))
>> AM.Disp = Disp;
>> else
>> - Reg = N.Val->getOperand(0);
>> + Reg = N.getNode()->getOperand(0);
>> } else {
>> - Reg = N.Val->getOperand(0);
>> + Reg = N.getNode()->getOperand(0);
>> }
>>
>> AM.IndexReg = AM.Base.Reg = Reg;
>> @@ -930,12 +930,12 @@
>> case ISD::ADD:
>> if (!AlreadySelected) {
>> X86ISelAddressMode Backup = AM;
>> - if (!MatchAddress(N.Val->getOperand(0), AM, false, Depth+1) &&
>> - !MatchAddress(N.Val->getOperand(1), AM, false, Depth+1))
>> + if (!MatchAddress(N.getNode()->getOperand(0), AM, false, Depth
>> +1) &&
>> + !MatchAddress(N.getNode()->getOperand(1), AM, false, Depth
>> +1))
>> return false;
>> AM = Backup;
>> - if (!MatchAddress(N.Val->getOperand(1), AM, false, Depth+1) &&
>> - !MatchAddress(N.Val->getOperand(0), AM, false, Depth+1))
>> + if (!MatchAddress(N.getNode()->getOperand(1), AM, false, Depth
>> +1) &&
>> + !MatchAddress(N.getNode()->getOperand(0), AM, false, Depth
>> +1))
>> return false;
>> AM = Backup;
>> }
>> @@ -970,7 +970,7 @@
>> if (Shift.getOpcode() != ISD::SHL) break;
>>
>> // Scale must not be used already.
>> - if (AM.IndexReg.Val != 0 || AM.Scale != 1) break;
>> + if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
>>
>> // Not when RIP is used as the base.
>> if (AM.isRIPRel) break;
>> @@ -995,8 +995,8 @@
>> SDValue(C2, 0),
>> SDValue(C1, 0));
>> SDValue NewAND = CurDAG->getNode(ISD::AND, N.getValueType(),
>> Shift.getOperand(0),
>> NewANDMask);
>> - NewANDMask.Val->setNodeId(Shift.Val->getNodeId());
>> - NewAND.Val->setNodeId(N.Val->getNodeId());
>> + NewANDMask.getNode()->setNodeId(Shift.getNode()->getNodeId());
>> + NewAND.getNode()->setNodeId(N.getNode()->getNodeId());
>>
>> AM.Scale = 1 << ShiftCst;
>> AM.IndexReg = NewAND;
>> @@ -1012,9 +1012,9 @@
>> bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode
>> &AM,
>> bool isRoot, unsigned Depth) {
>> // Is the base register already occupied?
>> - if (AM.BaseType != X86ISelAddressMode::RegBase ||
>> AM.Base.Reg.Val) {
>> + if (AM.BaseType != X86ISelAddressMode::RegBase ||
>> AM.Base.Reg.getNode()) {
>> // If so, check to see if the scale index register is set.
>> - if (AM.IndexReg.Val == 0 && !AM.isRIPRel) {
>> + if (AM.IndexReg.getNode() == 0 && !AM.isRIPRel) {
>> AM.IndexReg = N;
>> AM.Scale = 1;
>> return false;
>> @@ -1042,11 +1042,11 @@
>>
>> MVT VT = N.getValueType();
>> if (AM.BaseType == X86ISelAddressMode::RegBase) {
>> - if (!AM.Base.Reg.Val)
>> + if (!AM.Base.Reg.getNode())
>> AM.Base.Reg = CurDAG->getRegister(0, VT);
>> }
>>
>> - if (!AM.IndexReg.Val)
>> + if (!AM.IndexReg.getNode())
>> AM.IndexReg = CurDAG->getRegister(0, VT);
>>
>> getAddressOperands(AM, Base, Scale, Index, Disp);
>> @@ -1073,10 +1073,10 @@
>> SDValue &OutChain) {
>> if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
>> InChain = N.getOperand(0).getValue(1);
>> - if (ISD::isNON_EXTLoad(InChain.Val) &&
>> + if (ISD::isNON_EXTLoad(InChain.getNode()) &&
>> InChain.getValue(0).hasOneUse() &&
>> N.hasOneUse() &&
>> - CanBeFoldedBy(N.Val, Pred.Val, Op.Val)) {
>> + CanBeFoldedBy(N.getNode(), Pred.getNode(), Op.getNode())) {
>> LoadSDNode *LD = cast<LoadSDNode>(InChain);
>> if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
>> return false;
>> @@ -1087,11 +1087,11 @@
>>
>> // Also handle the case where we explicitly require zeros in the top
>> // elements. This is a vector shuffle from the zero vector.
>> - if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.Val->hasOneUse() &&
>> + if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()-
>>> hasOneUse() &&
>> // Check to see if the top elements are all zeros (or bitcast
>> of zeros).
>> N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
>> - N.getOperand(0).Val->hasOneUse() &&
>> - ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).Val) &&
>> + N.getOperand(0).getNode()->hasOneUse() &&
>> + ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
>> N.getOperand(0).getOperand(0).hasOneUse()) {
>> // Okay, this is a zero extending load. Fold it.
>> LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
>> @@ -1117,14 +1117,14 @@
>> MVT VT = N.getValueType();
>> unsigned Complexity = 0;
>> if (AM.BaseType == X86ISelAddressMode::RegBase)
>> - if (AM.Base.Reg.Val)
>> + if (AM.Base.Reg.getNode())
>> Complexity = 1;
>> else
>> AM.Base.Reg = CurDAG->getRegister(0, VT);
>> else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
>> Complexity = 4;
>>
>> - if (AM.IndexReg.Val)
>> + if (AM.IndexReg.getNode())
>> Complexity++;
>> else
>> AM.IndexReg = CurDAG->getRegister(0, VT);
>> @@ -1148,7 +1148,7 @@
>> Complexity += 2;
>> }
>>
>> - if (AM.Disp && (AM.Base.Reg.Val || AM.IndexReg.Val))
>> + if (AM.Disp && (AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
>> Complexity++;
>>
>> if (Complexity > 2) {
>> @@ -1161,9 +1161,9 @@
>> bool X86DAGToDAGISel::TryFoldLoad(SDValue P, SDValue N,
>> SDValue &Base, SDValue &Scale,
>> SDValue &Index, SDValue &Disp) {
>> - if (ISD::isNON_EXTLoad(N.Val) &&
>> + if (ISD::isNON_EXTLoad(N.getNode()) &&
>> N.hasOneUse() &&
>> - CanBeFoldedBy(N.Val, P.Val, P.Val))
>> + CanBeFoldedBy(N.getNode(), P.getNode(), P.getNode()))
>> return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp);
>> return false;
>> }
>> @@ -1198,14 +1198,14 @@
>> }
>>
>> }
>> - return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).Val;
>> + return CurDAG->getRegister(GlobalBaseReg,
>> TLI.getPointerTy()).getNode();
>> }
>>
>> static SDNode *FindCallStartFromCall(SDNode *Node) {
>> if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
>> assert(Node->getOperand(0).getValueType() == MVT::Other &&
>> "Node doesn't have a token chain argument!");
>> - return FindCallStartFromCall(Node->getOperand(0).Val);
>> + return FindCallStartFromCall(Node->getOperand(0).getNode());
>> }
>>
>> /// getTruncateTo8Bit - return an SDNode that implements a subreg
>> based
>> @@ -1239,7 +1239,7 @@
>>
>>
>> SDNode *X86DAGToDAGISel::Select(SDValue N) {
>> - SDNode *Node = N.Val;
>> + SDNode *Node = N.getNode();
>> MVT NVT = Node->getValueType(0);
>> unsigned Opc, MOpc;
>> unsigned Opcode = Node->getOpcode();
>> @@ -1277,7 +1277,7 @@
>> MVT PtrVT = TLI.getPointerTy();
>> SDValue N0 = N.getOperand(0);
>> SDValue N1 = N.getOperand(1);
>> - if (N.Val->getValueType(0) == PtrVT &&
>> + if (N.getNode()->getValueType(0) == PtrVT &&
>> N0.getOpcode() == X86ISD::Wrapper &&
>> N1.getOpcode() == ISD::Constant) {
>> unsigned Offset = (unsigned)cast<ConstantSDNode>(N1)-
>>> getValue();
>> @@ -1294,13 +1294,13 @@
>> CP->getOffset()+Offset);
>> }
>>
>> - if (C.Val) {
>> + if (C.getNode()) {
>> if (Subtarget->is64Bit()) {
>> SDValue Ops[] = { CurDAG->getRegister(0, PtrVT),
>> getI8Imm(1),
>> CurDAG->getRegister(0, PtrVT), C };
>> - return CurDAG->SelectNodeTo(N.Val, X86::LEA64r,
>> MVT::i64, Ops, 4);
>> + return CurDAG->SelectNodeTo(N.getNode(), X86::LEA64r,
>> MVT::i64, Ops, 4);
>> } else
>> - return CurDAG->SelectNodeTo(N.Val, X86::MOV32ri, PtrVT,
>> C);
>> + return CurDAG->SelectNodeTo(N.getNode(), X86::MOV32ri,
>> PtrVT, C);
>> }
>> }
>>
>> @@ -1379,7 +1379,7 @@
>> ReplaceUses(N.getValue(0), Result);
>> #ifndef NDEBUG
>> DOUT << std::string(Indent-2, ' ') << "=> ";
>> - DEBUG(Result.Val->dump(CurDAG));
>> + DEBUG(Result.getNode()->dump(CurDAG));
>> DOUT << "\n";
>> #endif
>> }
>> @@ -1406,7 +1406,7 @@
>> ReplaceUses(N.getValue(1), Result);
>> #ifndef NDEBUG
>> DOUT << std::string(Indent-2, ' ') << "=> ";
>> - DEBUG(Result.Val->dump(CurDAG));
>> + DEBUG(Result.getNode()->dump(CurDAG));
>> DOUT << "\n";
>> #endif
>> }
>> @@ -1538,7 +1538,7 @@
>> ReplaceUses(N.getValue(0), Result);
>> #ifndef NDEBUG
>> DOUT << std::string(Indent-2, ' ') << "=> ";
>> - DEBUG(Result.Val->dump(CurDAG));
>> + DEBUG(Result.getNode()->dump(CurDAG));
>> DOUT << "\n";
>> #endif
>> }
>> @@ -1565,7 +1565,7 @@
>> ReplaceUses(N.getValue(1), Result);
>> #ifndef NDEBUG
>> DOUT << std::string(Indent-2, ' ') << "=> ";
>> - DEBUG(Result.Val->dump(CurDAG));
>> + DEBUG(Result.getNode()->dump(CurDAG));
>> DOUT << "\n";
>> #endif
>> }
>> @@ -1599,7 +1599,7 @@
>>
>> #ifndef NDEBUG
>> DOUT << std::string(Indent-2, ' ') << "=> ";
>> - DEBUG(TruncOp.Val->dump(CurDAG));
>> + DEBUG(TruncOp.getNode()->dump(CurDAG));
>> DOUT << "\n";
>> DOUT << std::string(Indent-2, ' ') << "=> ";
>> DEBUG(ResNode->dump(CurDAG));
>> @@ -1659,8 +1659,8 @@
>>
>> #ifndef NDEBUG
>> DOUT << std::string(Indent-2, ' ') << "=> ";
>> - if (ResNode == NULL || ResNode == N.Val)
>> - DEBUG(N.Val->dump(CurDAG));
>> + if (ResNode == NULL || ResNode == N.getNode())
>> + DEBUG(N.getNode()->dump(CurDAG));
>> else
>> DEBUG(ResNode->dump(CurDAG));
>> DOUT << "\n";
>>
>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -852,7 +852,7 @@
>> unsigned CC = DAG.getMachineFunction().getFunction()-
>>> getCallingConv();
>> bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
>> CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
>> - CCInfo.AnalyzeReturn(Op.Val, RetCC_X86);
>> + CCInfo.AnalyzeReturn(Op.getNode(), RetCC_X86);
>>
>> // If this is the first return lowered for this function, add the
>> regs to the
>> // liveout set for the function.
>> @@ -944,7 +944,7 @@
>> RetOps[0] = Chain; // Update chain.
>>
>> // Add the flag if we have it.
>> - if (Flag.Val)
>> + if (Flag.getNode())
>> RetOps.push_back(Flag);
>>
>> return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, &RetOps[0],
>> RetOps.size());
>> @@ -1000,7 +1000,7 @@
>> // Merge everything together with a MERGE_VALUES node.
>> ResultVals.push_back(Chain);
>> return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
>> - ResultVals.size()).Val;
>> + ResultVals.size()).getNode();
>> }
>>
>>
>> @@ -1038,7 +1038,7 @@
>> /// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node
>> uses struct
>> /// return semantics.
>> static bool ArgsAreStructReturn(SDValue Op) {
>> - unsigned NumArgs = Op.Val->getNumValues() - 1;
>> + unsigned NumArgs = Op.getNode()->getNumValues() - 1;
>> if (!NumArgs)
>> return false;
>>
>> @@ -1182,7 +1182,7 @@
>> // Assign locations to all of the incoming arguments.
>> SmallVector<CCValAssign, 16> ArgLocs;
>> CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
>> - CCInfo.AnalyzeFormalArguments(Op.Val, CCAssignFnForNode(Op));
>> + CCInfo.AnalyzeFormalArguments(Op.getNode(),
>> CCAssignFnForNode(Op));
>>
>> SmallVector<SDValue, 8> ArgValues;
>> unsigned LastVal = ~0U;
>> @@ -1395,7 +1395,7 @@
>> FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
>>
>> // Return the new list of results.
>> - return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
>> + return DAG.getMergeValues(Op.getNode()->getVTList(),
>> &ArgValues[0],
>> ArgValues.size()).getValue(Op.getResNo());
>> }
>>
>> @@ -1433,7 +1433,7 @@
>> OutRetAddr = getReturnAddressFrameIndex(DAG);
>> // Load the "old" Return address.
>> OutRetAddr = DAG.getLoad(VT, Chain,OutRetAddr, NULL, 0);
>> - return SDValue(OutRetAddr.Val, 1);
>> + return SDValue(OutRetAddr.getNode(), 1);
>> }
>>
>> /// EmitTailCallStoreRetAddr - Emit a store of the return adress if
>> tail call
>> @@ -1472,7 +1472,7 @@
>> // Analyze operands of the call, assigning locations to each
>> operand.
>> SmallVector<CCValAssign, 16> ArgLocs;
>> CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
>> - CCInfo.AnalyzeCallOperands(Op.Val, CCAssignFnForNode(Op));
>> + CCInfo.AnalyzeCallOperands(Op.getNode(), CCAssignFnForNode(Op));
>>
>> // Get a count of how many bytes are to be pushed on the stack.
>> unsigned NumBytes = CCInfo.getNextStackOffset();
>> @@ -1562,7 +1562,7 @@
>> } else {
>> if (!IsTailCall || (IsTailCall && isByVal)) {
>> assert(VA.isMemLoc());
>> - if (StackPtr.Val == 0)
>> + if (StackPtr.getNode() == 0)
>> StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr,
>> getPointerTy());
>>
>> MemOpChains.push_back(LowerMemOpCallTo(Op, DAG, StackPtr,
>> VA, Chain,
>> @@ -1658,7 +1658,7 @@
>> if (Flags.isByVal()) {
>> // Copy relative to framepointer.
>> SDValue Source =
>> DAG.getIntPtrConstant(VA.getLocMemOffset());
>> - if (StackPtr.Val == 0)
>> + if (StackPtr.getNode() == 0)
>> StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr,
>> getPointerTy());
>> Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr,
>> Source);
>>
>> @@ -1719,7 +1719,7 @@
>> Ops.push_back(Chain);
>> Ops.push_back(DAG.getIntPtrConstant(NumBytes));
>> Ops.push_back(DAG.getIntPtrConstant(0));
>> - if (InFlag.Val)
>> + if (InFlag.getNode())
>> Ops.push_back(InFlag);
>> Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0],
>> Ops.size());
>> InFlag = Chain.getValue(1);
>> @@ -1751,16 +1751,16 @@
>> if (Is64Bit && isVarArg)
>> Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
>>
>> - if (InFlag.Val)
>> + if (InFlag.getNode())
>> Ops.push_back(InFlag);
>>
>> if (IsTailCall) {
>> - assert(InFlag.Val &&
>> + assert(InFlag.getNode() &&
>> "Flag must be set. Depend on flag being set in LowerRET");
>> Chain = DAG.getNode(X86ISD::TAILCALL,
>> - Op.Val->getVTList(), &Ops[0], Ops.size());
>> + Op.getNode()->getVTList(), &Ops[0],
>> Ops.size());
>>
>> - return SDValue(Chain.Val, Op.getResNo());
>> + return SDValue(Chain.getNode(), Op.getResNo());
>> }
>>
>> Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size());
>> @@ -1787,7 +1787,7 @@
>>
>> // Handle result values, copying them out of physregs into vregs
>> that we
>> // return.
>> - return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG),
>> Op.getResNo());
>> + return SDValue(LowerCallResult(Chain, InFlag, Op.getNode(), CC,
>> DAG), Op.getResNo());
>> }
>>
>>
>> @@ -2457,7 +2457,7 @@
>> }
>> }
>>
>> - if (!ElementBase.Val)
>> + if (!ElementBase.getNode())
>> return false;
>>
>> for (; i != NumElems; ++i) {
>> @@ -2661,7 +2661,7 @@
>> /// required.
>> static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
>> if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
>> - N = N->getOperand(0).Val;
>> + N = N->getOperand(0).getNode();
>> if (ISD::isNON_EXTLoad(N)) {
>> if (LD)
>> *LD = cast<LoadSDNode>(N);
>> @@ -2758,18 +2758,18 @@
>>
>> unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
>> if (Idx < NumElems) {
>> - unsigned Opc = V1.Val->getOpcode();
>> - if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.Val))
>> + unsigned Opc = V1.getNode()->getOpcode();
>> + if (Opc == ISD::UNDEF ||
>> ISD::isBuildVectorAllZeros(V1.getNode()))
>> continue;
>> if (Opc != ISD::BUILD_VECTOR ||
>> - !isZeroNode(V1.Val->getOperand(Idx)))
>> + !isZeroNode(V1.getNode()->getOperand(Idx)))
>> return false;
>> } else if (Idx >= NumElems) {
>> - unsigned Opc = V2.Val->getOpcode();
>> - if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.Val))
>> + unsigned Opc = V2.getNode()->getOpcode();
>> + if (Opc == ISD::UNDEF ||
>> ISD::isBuildVectorAllZeros(V2.getNode()))
>> continue;
>> if (Opc != ISD::BUILD_VECTOR ||
>> - !isZeroNode(V2.Val->getOperand(Idx - NumElems)))
>> + !isZeroNode(V2.getNode()->getOperand(Idx - NumElems)))
>> return false;
>> }
>> }
>> @@ -2958,8 +2958,8 @@
>> ++NumZeros;
>> continue;
>> }
>> - SDValue Elt = DAG.getShuffleScalarElt(Op.Val, Index);
>> - if (Elt.Val && isZeroNode(Elt))
>> + SDValue Elt = DAG.getShuffleScalarElt(Op.getNode(), Index);
>> + if (Elt.getNode() && isZeroNode(Elt))
>> ++NumZeros;
>> else
>> break;
>> @@ -3043,7 +3043,7 @@
>> } else
>> ThisElt = LastElt;
>>
>> - if (ThisElt.Val)
>> + if (ThisElt.getNode())
>> V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V,
>> ThisElt,
>> DAG.getIntPtrConstant(i/2));
>> }
>> @@ -3097,14 +3097,14 @@
>> SDValue
>> X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
>> // All zero's are handled with pxor, all one's are handled with
>> pcmpeqd.
>> - if (ISD::isBuildVectorAllZeros(Op.Val) ||
>> ISD::isBuildVectorAllOnes(Op.Val)) {
>> + if (ISD::isBuildVectorAllZeros(Op.getNode()) ||
>> ISD::isBuildVectorAllOnes(Op.getNode())) {
>> // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs
>> MMX) to
>> // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64
>> scalars are
>> // eliminated on x86-32 hosts.
>> if (Op.getValueType() == MVT::v4i32 || Op.getValueType() ==
>> MVT::v2i32)
>> return Op;
>>
>> - if (ISD::isBuildVectorAllOnes(Op.Val))
>> + if (ISD::isBuildVectorAllOnes(Op.getNode()))
>> return getOnesVector(Op.getValueType(), DAG);
>> return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(),
>> DAG);
>> }
>> @@ -3252,13 +3252,13 @@
>> if (EVTBits == 8 && NumElems == 16) {
>> SDValue V = LowerBuildVectorv16i8(Op,
>> NonZeros,NumNonZero,NumZero, DAG,
>> *this);
>> - if (V.Val) return V;
>> + if (V.getNode()) return V;
>> }
>>
>> if (EVTBits == 16 && NumElems == 8) {
>> SDValue V = LowerBuildVectorv8i16(Op,
>> NonZeros,NumNonZero,NumZero, DAG,
>> *this);
>> - if (V.Val) return V;
>> + if (V.getNode()) return V;
>> }
>>
>> // If element VT is == 32 bits, turn it into a number of shuffles.
>> @@ -3344,8 +3344,8 @@
>> MVT MaskVT = MVT::getIntVectorWithNumElements(8);
>> MVT MaskEVT = MaskVT.getVectorElementType();
>> MVT PtrVT = TLI.getPointerTy();
>> - SmallVector<SDValue, 8> MaskElts(PermMask.Val->op_begin(),
>> - PermMask.Val->op_end());
>> + SmallVector<SDValue, 8> MaskElts(PermMask.getNode()->op_begin(),
>> + PermMask.getNode()->op_end());
>>
>> // First record which half of which vector the low elements come
>> from.
>> SmallVector<unsigned, 4> LowQuad(4);
>> @@ -3653,7 +3653,7 @@
>> const X86Subtarget *Subtarget) {
>> if (VT == MVT::v2f64 || VT == MVT::v4f32) {
>> LoadSDNode *LD = NULL;
>> - if (!isScalarLoadToVector(SrcOp.Val, &LD))
>> + if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
>> LD = dyn_cast<LoadSDNode>(SrcOp);
>> if (!LD) {
>> // movssrr and movsdrr do not clear top bits. Try to use movd,
>> movq
>> @@ -3850,18 +3850,18 @@
>> bool V1IsSplat = false;
>> bool V2IsSplat = false;
>>
>> - if (isUndefShuffle(Op.Val))
>> + if (isUndefShuffle(Op.getNode()))
>> return DAG.getNode(ISD::UNDEF, VT);
>>
>> - if (isZeroShuffle(Op.Val))
>> + if (isZeroShuffle(Op.getNode()))
>> return getZeroVector(VT, Subtarget->hasSSE2(), DAG);
>>
>> - if (isIdentityMask(PermMask.Val))
>> + if (isIdentityMask(PermMask.getNode()))
>> return V1;
>> - else if (isIdentityMask(PermMask.Val, true))
>> + else if (isIdentityMask(PermMask.getNode(), true))
>> return V2;
>>
>> - if (isSplatMask(PermMask.Val)) {
>> + if (isSplatMask(PermMask.getNode())) {
>> if (isMMX || NumElems < 4) return Op;
>> // Promote it to a v4{if}32 splat.
>> return PromoteSplat(Op, DAG, Subtarget->hasSSE2());
>> @@ -3871,27 +3871,27 @@
>> // do it!
>> if (VT == MVT::v8i16 || VT == MVT::v16i8) {
>> SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
>> DAG, *this);
>> - if (NewOp.Val)
>> + if (NewOp.getNode())
>> return DAG.getNode(ISD::BIT_CONVERT, VT,
>> LowerVECTOR_SHUFFLE(NewOp, DAG));
>> } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget-
>>> hasSSE2()))) {
>> // FIXME: Figure out a cleaner way to do this.
>> // Try to make use of movq to zero out the top part.
>> - if (ISD::isBuildVectorAllZeros(V2.Val)) {
>> + if (ISD::isBuildVectorAllZeros(V2.getNode())) {
>> SDValue NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
>> DAG, *this);
>> - if (NewOp.Val) {
>> + if (NewOp.getNode()) {
>> SDValue NewV1 = NewOp.getOperand(0);
>> SDValue NewV2 = NewOp.getOperand(1);
>> SDValue NewMask = NewOp.getOperand(2);
>> - if (isCommutedMOVL(NewMask.Val, true, false)) {
>> + if (isCommutedMOVL(NewMask.getNode(), true, false)) {
>> NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask,
>> DAG);
>> return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG,
>> Subtarget);
>> }
>> }
>> - } else if (ISD::isBuildVectorAllZeros(V1.Val)) {
>> + } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
>> SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
>> DAG, *this);
>> - if (NewOp.Val && X86::isMOVLMask(NewOp.getOperand(2).Val))
>> + if (NewOp.getNode() &&
>> X86::isMOVLMask(NewOp.getOperand(2).getNode()))
>> return getVZextMovL(VT, NewOp.getValueType(),
>> NewOp.getOperand(1),
>> DAG, Subtarget);
>> }
>> @@ -3910,24 +3910,24 @@
>> return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
>> }
>>
>> - if (X86::isMOVLMask(PermMask.Val)) {
>> + if (X86::isMOVLMask(PermMask.getNode())) {
>> if (V1IsUndef)
>> return V2;
>> - if (ISD::isBuildVectorAllZeros(V1.Val))
>> + if (ISD::isBuildVectorAllZeros(V1.getNode()))
>> return getVZextMovL(VT, VT, V2, DAG, Subtarget);
>> if (!isMMX)
>> return Op;
>> }
>>
>> - if (!isMMX && (X86::isMOVSHDUPMask(PermMask.Val) ||
>> - X86::isMOVSLDUPMask(PermMask.Val) ||
>> - X86::isMOVHLPSMask(PermMask.Val) ||
>> - X86::isMOVHPMask(PermMask.Val) ||
>> - X86::isMOVLPMask(PermMask.Val)))
>> + if (!isMMX && (X86::isMOVSHDUPMask(PermMask.getNode()) ||
>> + X86::isMOVSLDUPMask(PermMask.getNode()) ||
>> + X86::isMOVHLPSMask(PermMask.getNode()) ||
>> + X86::isMOVHPMask(PermMask.getNode()) ||
>> + X86::isMOVLPMask(PermMask.getNode())))
>> return Op;
>>
>> - if (ShouldXformToMOVHLPS(PermMask.Val) ||
>> - ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val))
>> + if (ShouldXformToMOVHLPS(PermMask.getNode()) ||
>> + ShouldXformToMOVLP(V1.getNode(), V2.getNode(),
>> PermMask.getNode()))
>> return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
>>
>> if (isShift) {
>> @@ -3940,8 +3940,8 @@
>> bool Commuted = false;
>> // FIXME: This should also accept a bitcast of a splat? Be
>> careful, not
>> // 1,1,1,1 -> v8i16 though.
>> - V1IsSplat = isSplatVector(V1.Val);
>> - V2IsSplat = isSplatVector(V2.Val);
>> + V1IsSplat = isSplatVector(V1.getNode());
>> + V2IsSplat = isSplatVector(V2.getNode());
>>
>> // Canonicalize the splat or undef, if present, to be on the RHS.
>> if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
>> @@ -3952,7 +3952,7 @@
>> }
>>
>> // FIXME: Figure out a cleaner way to do this.
>> - if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
>> + if (isCommutedMOVL(PermMask.getNode(), V2IsSplat, V2IsUndef)) {
>> if (V2IsUndef) return V1;
>> Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
>> if (V2IsSplat) {
>> @@ -3960,16 +3960,16 @@
>> // to any V2 element. The instruction selectior won't like
>> this. Get
>> // a corrected mask and commute to form a proper MOVS{S|D}.
>> SDValue NewMask = getMOVLMask(NumElems, DAG);
>> - if (NewMask.Val != PermMask.Val)
>> + if (NewMask.getNode() != PermMask.getNode())
>> Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
>> }
>> return Op;
>> }
>>
>> - if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
>> - X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
>> - X86::isUNPCKLMask(PermMask.Val) ||
>> - X86::isUNPCKHMask(PermMask.Val))
>> + if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
>> + X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
>> + X86::isUNPCKLMask(PermMask.getNode()) ||
>> + X86::isUNPCKHMask(PermMask.getNode()))
>> return Op;
>>
>> if (V2IsSplat) {
>> @@ -3977,11 +3977,11 @@
>> // element then try to match unpck{h|l} again. If match, return a
>> // new vector_shuffle with the corrected mask.
>> SDValue NewMask = NormalizeMask(PermMask, DAG);
>> - if (NewMask.Val != PermMask.Val) {
>> - if (X86::isUNPCKLMask(PermMask.Val, true)) {
>> + if (NewMask.getNode() != PermMask.getNode()) {
>> + if (X86::isUNPCKLMask(PermMask.getNode(), true)) {
>> SDValue NewMask = getUnpacklMask(NumElems, DAG);
>> return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
>> - } else if (X86::isUNPCKHMask(PermMask.Val, true)) {
>> + } else if (X86::isUNPCKHMask(PermMask.getNode(), true)) {
>> SDValue NewMask = getUnpackhMask(NumElems, DAG);
>> return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
>> }
>> @@ -3989,23 +3989,23 @@
>> }
>>
>> // Normalize the node to match x86 shuffle ops if needed
>> - if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val))
>> + if (V2.getOpcode() != ISD::UNDEF &&
>> isCommutedSHUFP(PermMask.getNode()))
>> Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
>>
>> if (Commuted) {
>> // Commute is back and try unpck* again.
>> Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
>> - if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
>> - X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
>> - X86::isUNPCKLMask(PermMask.Val) ||
>> - X86::isUNPCKHMask(PermMask.Val))
>> + if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
>> + X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
>> + X86::isUNPCKLMask(PermMask.getNode()) ||
>> + X86::isUNPCKHMask(PermMask.getNode()))
>> return Op;
>> }
>>
>> // Try PSHUF* first, then SHUFP*.
>> // MMX doesn't have PSHUFD but it does have PSHUFW. While it's
>> theoretically
>> // possible to shuffle a v2i32 using PSHUFW, that's not yet
>> implemented.
>> - if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.Val)) {
>> + if (isMMX && NumElems == 4 &&
>> X86::isPSHUFDMask(PermMask.getNode())) {
>> if (V2.getOpcode() != ISD::UNDEF)
>> return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
>> DAG.getNode(ISD::UNDEF, VT), PermMask);
>> @@ -4014,9 +4014,9 @@
>>
>> if (!isMMX) {
>> if (Subtarget->hasSSE2() &&
>> - (X86::isPSHUFDMask(PermMask.Val) ||
>> - X86::isPSHUFHWMask(PermMask.Val) ||
>> - X86::isPSHUFLWMask(PermMask.Val))) {
>> + (X86::isPSHUFDMask(PermMask.getNode()) ||
>> + X86::isPSHUFHWMask(PermMask.getNode()) ||
>> + X86::isPSHUFLWMask(PermMask.getNode()))) {
>> MVT RVT = VT;
>> if (VT == MVT::v4f32) {
>> RVT = MVT::v4i32;
>> @@ -4032,15 +4032,15 @@
>> }
>>
>> // Binary or unary shufps.
>> - if (X86::isSHUFPMask(PermMask.Val) ||
>> - (V2.getOpcode() == ISD::UNDEF &&
>> X86::isPSHUFDMask(PermMask.Val)))
>> + if (X86::isSHUFPMask(PermMask.getNode()) ||
>> + (V2.getOpcode() == ISD::UNDEF &&
>> X86::isPSHUFDMask(PermMask.getNode())))
>> return Op;
>> }
>>
>> // Handle v8i16 specifically since SSE can do byte extraction and
>> insertion.
>> if (VT == MVT::v8i16) {
>> SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG,
>> *this);
>> - if (NewOp.Val)
>> + if (NewOp.getNode())
>> return NewOp;
>> }
>>
>> @@ -4073,7 +4073,7 @@
>> // result has a single use which is a store or a bitcast to i32.
>> if (!Op.hasOneUse())
>> return SDValue();
>> - SDNode *User = *Op.Val->use_begin();
>> + SDNode *User = *Op.getNode()->use_begin();
>> if (User->getOpcode() != ISD::STORE &&
>> (User->getOpcode() != ISD::BIT_CONVERT ||
>> User->getValueType(0) != MVT::i32))
>> @@ -4094,7 +4094,7 @@
>>
>> if (Subtarget->hasSSE41()) {
>> SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
>> - if (Res.Val)
>> + if (Res.getNode())
>> return Res;
>> }
>>
>> @@ -4599,7 +4599,7 @@
>> SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG
>> &DAG) {
>> std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(Op, DAG);
>> SDValue FIST = Vals.first, StackSlot = Vals.second;
>> - if (FIST.Val == 0) return SDValue();
>> + if (FIST.getNode() == 0) return SDValue();
>>
>> // Load the result.
>> return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
>> @@ -4608,7 +4608,7 @@
>> SDNode *X86TargetLowering::ExpandFP_TO_SINT(SDNode *N, SelectionDAG
>> &DAG) {
>> std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(SDValue(N, 0),
>> DAG);
>> SDValue FIST = Vals.first, StackSlot = Vals.second;
>> - if (FIST.Val == 0) return 0;
>> + if (FIST.getNode() == 0) return 0;
>>
>> MVT VT = N->getValueType(0);
>>
>> @@ -4618,7 +4618,7 @@
>> // Use MERGE_VALUES to drop the chain result value and get a node
>> with one
>> // result. This requires turning off getMergeValues
>> simplification, since
>> // otherwise it will give us Res back.
>> - return DAG.getMergeValues(&Res, 1, false).Val;
>> + return DAG.getMergeValues(&Res, 1, false).getNode();
>> }
>>
>> SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
>> @@ -5258,7 +5258,7 @@
>> DAG.getNode(ISD::OR, MVT::i64, rax, Tmp), rdx.getValue(1)
>> };
>>
>> - return DAG.getMergeValues(Ops, 2).Val;
>> + return DAG.getMergeValues(Ops, 2).getNode();
>> }
>>
>> SDValue eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32,
>> rd.getValue(1));
>> @@ -5270,7 +5270,7 @@
>>
>> // Use a MERGE_VALUES to return the value and chain.
>> Ops[1] = edx.getValue(1);
>> - return DAG.getMergeValues(Ops, 2).Val;
>> + return DAG.getMergeValues(Ops, 2).getNode();
>> }
>>
>> SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG
>> &DAG) {
>> @@ -5857,7 +5857,7 @@
>> if (Subtarget->is64Bit()) {
>> Reg = X86::RAX; size = 8;
>> } else //Should go away when LowerType stuff lands
>> - return SDValue(ExpandATOMIC_CMP_SWAP(Op.Val, DAG), 0);
>> + return SDValue(ExpandATOMIC_CMP_SWAP(Op.getNode(), DAG), 0);
>> break;
>> };
>> SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg,
>> @@ -5907,7 +5907,7 @@
>> SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
>> SDValue ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2);
>> SDValue Vals[2] = { ResultVal, cpOutH.getValue(1) };
>> - return DAG.getMergeValues(Vals, 2).Val;
>> + return DAG.getMergeValues(Vals, 2).getNode();
>> }
>>
>> SDNode* X86TargetLowering::ExpandATOMIC_LOAD_SUB(SDNode* Op,
>> SelectionDAG &DAG) {
>> @@ -5920,7 +5920,7 @@
>> T==MVT::i64 ? ISD::ATOMIC_LOAD_ADD_64: 0),
>> Op->getOperand(0), Op->getOperand(1), negOp,
>> cast<AtomicSDNode>(Op)->getSrcValue(),
>> - cast<AtomicSDNode>(Op)->getAlignment()).Val;
>> + cast<AtomicSDNode>(Op)-
>>> getAlignment()).getNode();
>> }
>>
>> /// LowerOperation - Provide custom lowering hooks for some
>> operations.
>> @@ -5974,7 +5974,7 @@
>>
>> // FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands.
>> case ISD::READCYCLECOUNTER:
>> - return SDValue(ExpandREADCYCLECOUNTER(Op.Val, DAG), 0);
>> + return SDValue(ExpandREADCYCLECOUNTER(Op.getNode(), DAG), 0);
>> }
>> }
>>
>> @@ -6135,15 +6135,15 @@
>> X86TargetLowering::isShuffleMaskLegal(SDValue Mask, MVT VT) const {
>> // Only do shuffles on 128-bit vector types for now.
>> if (VT.getSizeInBits() == 64) return false;
>> - return (Mask.Val->getNumOperands() <= 4 ||
>> - isIdentityMask(Mask.Val) ||
>> - isIdentityMask(Mask.Val, true) ||
>> - isSplatMask(Mask.Val) ||
>> - isPSHUFHW_PSHUFLWMask(Mask.Val) ||
>> - X86::isUNPCKLMask(Mask.Val) ||
>> - X86::isUNPCKHMask(Mask.Val) ||
>> - X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
>> - X86::isUNPCKH_v_undef_Mask(Mask.Val));
>> + return (Mask.getNode()->getNumOperands() <= 4 ||
>> + isIdentityMask(Mask.getNode()) ||
>> + isIdentityMask(Mask.getNode(), true) ||
>> + isSplatMask(Mask.getNode()) ||
>> + isPSHUFHW_PSHUFLWMask(Mask.getNode()) ||
>> + X86::isUNPCKLMask(Mask.getNode()) ||
>> + X86::isUNPCKHMask(Mask.getNode()) ||
>> + X86::isUNPCKL_v_undef_Mask(Mask.getNode()) ||
>> + X86::isUNPCKH_v_undef_Mask(Mask.getNode()));
>> }
>>
>> bool
>> @@ -6695,11 +6695,11 @@
>> }
>>
>> SDValue Elt = DAG.getShuffleScalarElt(N, i);
>> - if (!Elt.Val ||
>> - (Elt.getOpcode() != ISD::UNDEF && !
>> ISD::isNON_EXTLoad(Elt.Val)))
>> + if (!Elt.getNode() ||
>> + (Elt.getOpcode() != ISD::UNDEF && !
>> ISD::isNON_EXTLoad(Elt.getNode())))
>> return false;
>> if (!Base) {
>> - Base = Elt.Val;
>> + Base = Elt.getNode();
>> if (Base->getOpcode() == ISD::UNDEF)
>> return false;
>> continue;
>> @@ -6707,7 +6707,7 @@
>> if (Elt.getOpcode() == ISD::UNDEF)
>> continue;
>>
>> - if (!TLI.isConsecutiveLoad(Elt.Val, Base,
>> + if (!TLI.isConsecutiveLoad(Elt.getNode(), Base,
>> EVT.getSizeInBits()/8, i, MFI))
>> return false;
>> }
>> @@ -6731,7 +6731,7 @@
>> return SDValue();
>>
>> LoadSDNode *LD = cast<LoadSDNode>(Base);
>> - if (isBaseAlignmentOfN(16, Base->getOperand(1).Val, TLI))
>> + if (isBaseAlignmentOfN(16, Base->getOperand(1).getNode(), TLI))
>> return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD-
>>> getSrcValue(),
>> LD->getSrcValueOffset(), LD->isVolatile());
>> return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD-
>>> getSrcValue(),
>> @@ -6762,11 +6762,11 @@
>> return SDValue();
>>
>> // Value must be a load.
>> - SDNode *Base = N->getOperand(0).Val;
>> + SDNode *Base = N->getOperand(0).getNode();
>> if (!isa<LoadSDNode>(Base)) {
>> if (Base->getOpcode() != ISD::BIT_CONVERT)
>> return SDValue();
>> - Base = Base->getOperand(0).Val;
>> + Base = Base->getOperand(0).getNode();
>> if (!isa<LoadSDNode>(Base))
>> return SDValue();
>> }
>> @@ -6866,11 +6866,11 @@
>> isa<LoadSDNode>(St->getValue()) &&
>> !cast<LoadSDNode>(St->getValue())->isVolatile() &&
>> St->getChain().hasOneUse() && !St->isVolatile()) {
>> - SDNode* LdVal = St->getValue().Val;
>> + SDNode* LdVal = St->getValue().getNode();
>> LoadSDNode *Ld = 0;
>> int TokenFactorIndex = -1;
>> SmallVector<SDValue, 8> Ops;
>> - SDNode* ChainVal = St->getChain().Val;
>> + SDNode* ChainVal = St->getChain().getNode();
>> // Must be a store of a load. We currently handle two cases:
>> the load
>> // is a direct child, and it's under an intervening
>> TokenFactor. It is
>> // possible to dig deeper under nested TokenFactors.
>> @@ -6879,7 +6879,7 @@
>> else if (St->getValue().hasOneUse() &&
>> ChainVal->getOpcode() == ISD::TokenFactor) {
>> for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; +
>> +i) {
>> - if (ChainVal->getOperand(i).Val == LdVal) {
>> + if (ChainVal->getOperand(i).getNode() == LdVal) {
>> TokenFactorIndex = i;
>> Ld = cast<LoadSDNode>(St->getValue());
>> } else
>> @@ -7108,7 +7108,7 @@
>> }
>> }
>>
>> - if (Result.Val) {
>> + if (Result.getNode()) {
>> Ops.push_back(Result);
>> return;
>> }
>>
>> Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
>> +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Thu Aug 28 16:40:38
>> 2008
>> @@ -506,17 +506,17 @@
>>
>> if (NeedCheck) {
>> std::string ParentName(RootName.begin(),
>> RootName.end()-1);
>> - emitCheck("CanBeFoldedBy(" + RootName + ".Val, " +
>> ParentName +
>> - ".Val, N.Val)");
>> + emitCheck("CanBeFoldedBy(" + RootName + ".getNode(), "
>> + ParentName +
>> + ".getNode(), N.getNode())");
>> }
>> }
>> }
>>
>> if (NodeHasChain) {
>> if (FoundChain) {
>> - emitCheck("(" + ChainName + ".Val == " + RootName + ".Val
>> || "
>> - "IsChainCompatible(" + ChainName + ".Val, " +
>> - RootName + ".Val))");
>> + emitCheck("(" + ChainName + ".getNode() == " + RootName +
>> ".getNode() || "
>> + "IsChainCompatible(" + ChainName + ".getNode(),
>> " +
>> + RootName + ".getNode()))");
>> OrigChains.push_back(std::make_pair(ChainName, RootName));
>> } else
>> FoundChain = true;
>> @@ -543,7 +543,7 @@
>>
>> // If there is a node predicate for this, emit the call.
>> if (!N->getPredicateFn().empty())
>> - emitCheck(N->getPredicateFn() + "(" + RootName + ".Val)");
>> + emitCheck(N->getPredicateFn() + "(" + RootName +
>> ".getNode())");
>>
>>
>> // If this is an 'and R, 1234' where the operation is AND/OR and
>> the RHS is
>> @@ -720,7 +720,7 @@
>> // If there is a node predicate for this, emit the call.
>> if (!Child->getPredicateFn().empty())
>> emitCheck(Child->getPredicateFn() + "(" + RootName +
>> - ".Val)");
>> + ".getNode())");
>> } else if (IntInit *II =
>> dynamic_cast<IntInit*>(Child->getLeafValue())) {
>> emitCheck("isa<ConstantSDNode>(" + RootName + ")");
>> @@ -951,8 +951,8 @@
>> // case, the TokenFactor can have more operands.
>> emitCode("SmallVector<SDValue, 8> InChains;");
>> for (unsigned i = 0, e = OrigChains.size(); i < e; ++i) {
>> - emitCode("if (" + OrigChains[i].first + ".Val != " +
>> - OrigChains[i].second + ".Val) {");
>> + emitCode("if (" + OrigChains[i].first + ".getNode() != " +
>> + OrigChains[i].second + ".getNode()) {");
>> emitCode(" AddToISelQueue(" + OrigChains[i].first + ");");
>> emitCode(" InChains.push_back(" + OrigChains[i].first +
>> ");");
>> emitCode("}");
>> @@ -1164,7 +1164,7 @@
>> std::string Code;
>> for (unsigned j = 0, e = FoldedChains.size(); j < e; j++) {
>> ReplaceFroms.push_back("SDValue(" +
>> - FoldedChains[j].first + ".Val, " +
>> + FoldedChains[j].first +
>> ".getNode(), " +
>> utostr(FoldedChains[j].second) +
>> ")");
>> ReplaceTos.push_back("SDValue(ResNode, " +
>> @@ -1174,12 +1174,12 @@
>>
>> if (NodeHasOutFlag) {
>> if (FoldedFlag.first != "") {
>> - ReplaceFroms.push_back("SDValue(" + FoldedFlag.first +
>> ".Val, " +
>> + ReplaceFroms.push_back("SDValue(" + FoldedFlag.first +
>> ".getNode(), " +
>> utostr(FoldedFlag.second) + ")");
>> ReplaceTos.push_back("InFlag");
>> } else {
>> assert(NodeHasProperty(Pattern, SDNPOutFlag, CGP));
>> - ReplaceFroms.push_back("SDValue(N.Val, " +
>> + ReplaceFroms.push_back("SDValue(N.getNode(), " +
>> utostr(NumPatResults +
>> (unsigned)InputHasChain)
>> + ")");
>> ReplaceTos.push_back("InFlag");
>> @@ -1187,9 +1187,9 @@
>> }
>>
>> if (!ReplaceFroms.empty() && InputHasChain) {
>> - ReplaceFroms.push_back("SDValue(N.Val, " +
>> + ReplaceFroms.push_back("SDValue(N.getNode(), " +
>> utostr(NumPatResults) + ")");
>> - ReplaceTos.push_back("SDValue(" + ChainName + ".Val, " +
>> + ReplaceTos.push_back("SDValue(" + ChainName + ".getNode(),
>> " +
>> ChainName + ".getResNo()" + ")");
>> ChainAssignmentNeeded |= NodeHasChain;
>> }
>> @@ -1200,12 +1200,12 @@
>> } else if (InputHasChain && !NodeHasChain) {
>> // One of the inner node produces a chain.
>> if (NodeHasOutFlag) {
>> - ReplaceFroms.push_back("SDValue(N.Val, " +
>> + ReplaceFroms.push_back("SDValue(N.getNode(), " +
>> utostr(NumPatResults+1) +
>> ")");
>> ReplaceTos.push_back("SDValue(ResNode, N.getResNo()-1)");
>> }
>> - ReplaceFroms.push_back("SDValue(N.Val, " +
>> + ReplaceFroms.push_back("SDValue(N.getNode(), " +
>> utostr(NumPatResults) + ")");
>> ReplaceTos.push_back(ChainName);
>> }
>> @@ -1216,7 +1216,7 @@
>> std::string ChainAssign;
>> if (!isRoot)
>> ChainAssign = ChainName + " = SDValue(" + NodeName +
>> - ".Val, " + utostr(NumResults+NumDstRegs) +
>> ");";
>> + ".getNode(), " + utostr(NumResults
>> +NumDstRegs) + ");";
>> else
>> ChainAssign = ChainName + " = SDValue(" + NodeName +
>> ", " + utostr(NumResults+NumDstRegs) + ");";
>> @@ -1251,7 +1251,7 @@
>> if (!isRoot || (InputHasChain && !NodeHasChain)) {
>> Code = "CurDAG->getTargetNode(" + Code;
>> } else {
>> - Code = "CurDAG->SelectNodeTo(N.Val, " + Code;
>> + Code = "CurDAG->SelectNodeTo(N.getNode(), " + Code;
>> }
>> if (isRoot) {
>> if (After.empty())
>> @@ -1274,10 +1274,10 @@
>> ResNodeDecled, true);
>> unsigned ResNo = TmpNo++;
>> emitCode("SDValue Tmp" + utostr(ResNo) + " = Transform_" + Op-
>>> getName()
>> - + "(" + Ops.back() + ".Val);");
>> + + "(" + Ops.back() + ".getNode());");
>> NodeOps.push_back("Tmp" + utostr(ResNo));
>> if (isRoot)
>> - emitCode("return Tmp" + utostr(ResNo) + ".Val;");
>> + emitCode("return Tmp" + utostr(ResNo) + ".getNode();");
>> return NodeOps;
>> } else {
>> N->dump();
>> @@ -1298,7 +1298,7 @@
>> Pat->setTypes(Other->getExtTypes());
>> // The top level node type is checked outside of the select
>> function.
>> if (!isRoot)
>> - emitCheck(Prefix + ".Val->getValueType(0) == " +
>> + emitCheck(Prefix + ".getNode()->getValueType(0) == " +
>> getName(Pat->getTypeNum(0)));
>> return true;
>> }
>> @@ -1360,7 +1360,7 @@
>> std::string Decl = (!ResNodeDecled) ? "SDNode *" : "";
>> emitCode(Decl + "ResNode = CurDAG->getCopyToReg(" +
>> ChainName +
>> ", " + getQualifiedName(RR) +
>> - ", " + RootName + utostr(OpNo) + ",
>> InFlag).Val;");
>> + ", " + RootName + utostr(OpNo) + ",
>> InFlag).getNode();");
>> ResNodeDecled = true;
>> emitCode(ChainName + " = SDValue(ResNode, 0);");
>> emitCode("InFlag = SDValue(ResNode, 1);");
>> @@ -1836,7 +1836,7 @@
>> if (OpName != "ISD::INTRINSIC_W_CHAIN" &&
>> OpName != "ISD::INTRINSIC_WO_CHAIN" &&
>> OpName != "ISD::INTRINSIC_VOID") {
>> - OS << " N.Val->dump(CurDAG);\n";
>> + OS << " N.getNode()->dump(CurDAG);\n";
>> } else {
>> OS << " unsigned iid = cast<ConstantSDNode>(N.getOperand("
>> "N.getOperand(0).getValueType() == MVT::Other))-
>>> getValue();\n"
>> @@ -1853,7 +1853,7 @@
>>
>> // Emit boilerplate.
>> OS << "SDNode *Select_INLINEASM(SDValue N) {\n"
>> - << " std::vector<SDValue> Ops(N.Val->op_begin(), N.Val-
>>> op_end());\n"
>> + << " std::vector<SDValue> Ops(N.getNode()->op_begin(),
>> N.getNode()->op_end());\n"
>> << " SelectInlineAsmMemoryOperands(Ops);\n\n"
>>
>> << " // Ensure that the asm operands are themselves selected.\n"
>> @@ -1865,11 +1865,11 @@
>> << " VTs.push_back(MVT::Flag);\n"
>> << " SDValue New = CurDAG->getNode(ISD::INLINEASM, VTs,
>> &Ops[0], "
>> "Ops.size());\n"
>> - << " return New.Val;\n"
>> + << " return New.getNode();\n"
>> << "}\n\n";
>>
>> OS << "SDNode *Select_UNDEF(const SDValue &N) {\n"
>> - << " return CurDAG->SelectNodeTo(N.Val,
>> TargetInstrInfo::IMPLICIT_DEF,\n"
>> + << " return CurDAG->SelectNodeTo(N.getNode(),
>> TargetInstrInfo::IMPLICIT_DEF,\n"
>> << " N.getValueType());\n"
>> << "}\n\n";
>>
>> @@ -1878,7 +1878,7 @@
>> << " unsigned C = cast<LabelSDNode>(N)->getLabelID();\n"
>> << " SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
>> << " AddToISelQueue(Chain);\n"
>> - << " return CurDAG->SelectNodeTo(N.Val,
>> TargetInstrInfo::DBG_LABEL,\n"
>> + << " return CurDAG->SelectNodeTo(N.getNode(),
>> TargetInstrInfo::DBG_LABEL,\n"
>> << " MVT::Other, Tmp, Chain);\n"
>> << "}\n\n";
>>
>> @@ -1887,7 +1887,7 @@
>> << " unsigned C = cast<LabelSDNode>(N)->getLabelID();\n"
>> << " SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
>> << " AddToISelQueue(Chain);\n"
>> - << " return CurDAG->SelectNodeTo(N.Val,
>> TargetInstrInfo::EH_LABEL,\n"
>> + << " return CurDAG->SelectNodeTo(N.getNode(),
>> TargetInstrInfo::EH_LABEL,\n"
>> << " MVT::Other, Tmp, Chain);\n"
>> << "}\n\n";
>>
>> @@ -1897,7 +1897,7 @@
>> << " SDValue N2 = N.getOperand(2);\n"
>> << " if (!isa<FrameIndexSDNode>(N1) || !
>> isa<GlobalAddressSDNode>(N2)) {\n"
>> << " cerr << \"Cannot yet select llvm.dbg.declare: \";\n"
>> - << " N.Val->dump(CurDAG);\n"
>> + << " N.getNode()->dump(CurDAG);\n"
>> << " abort();\n"
>> << " }\n"
>> << " int FI = cast<FrameIndexSDNode>(N1)->getIndex();\n"
>> @@ -1907,7 +1907,7 @@
>> << " SDValue Tmp2 = "
>> << "CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());\n"
>> << " AddToISelQueue(Chain);\n"
>> - << " return CurDAG->SelectNodeTo(N.Val,
>> TargetInstrInfo::DECLARE,\n"
>> + << " return CurDAG->SelectNodeTo(N.getNode(),
>> TargetInstrInfo::DECLARE,\n"
>> << " MVT::Other, Tmp1, Tmp2,
>> Chain);\n"
>> << "}\n\n";
>>
>> @@ -1917,7 +1917,7 @@
>> << " unsigned C = cast<ConstantSDNode>(N1)->getValue();\n"
>> << " SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
>> << " AddToISelQueue(N0);\n"
>> - << " return CurDAG->SelectNodeTo(N.Val,
>> TargetInstrInfo::EXTRACT_SUBREG,\n"
>> + << " return CurDAG->SelectNodeTo(N.getNode(),
>> TargetInstrInfo::EXTRACT_SUBREG,\n"
>> << " N.getValueType(), N0, Tmp);\n"
>> << "}\n\n";
>>
>> @@ -1929,7 +1929,7 @@
>> << " SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
>> << " AddToISelQueue(N1);\n"
>> << " AddToISelQueue(N0);\n"
>> - << " return CurDAG->SelectNodeTo(N.Val,
>> TargetInstrInfo::INSERT_SUBREG,\n"
>> + << " return CurDAG->SelectNodeTo(N.getNode(),
>> TargetInstrInfo::INSERT_SUBREG,\n"
>> << " N.getValueType(), N0, N1,
>> Tmp);\n"
>> << "}\n\n";
>>
>> @@ -1938,7 +1938,7 @@
>> << " if (N.isMachineOpcode()) {\n"
>> << " return NULL; // Already selected.\n"
>> << " }\n\n"
>> - << " MVT::SimpleValueType NVT = N.Val-
>>> getValueType(0).getSimpleVT();\n"
>> + << " MVT::SimpleValueType NVT = N.getNode()-
>>> getValueType(0).getSimpleVT();\n"
>> << " switch (N.getOpcode()) {\n"
>> << " default: break;\n"
>> << " case ISD::EntryToken: // These leaves remain the
>> same.\n"
>> @@ -2033,7 +2033,7 @@
>> << " if (N.getOpcode() != ISD::INTRINSIC_W_CHAIN &&\n"
>> << " N.getOpcode() != ISD::INTRINSIC_WO_CHAIN &&\n"
>> << " N.getOpcode() != ISD::INTRINSIC_VOID) {\n"
>> - << " N.Val->dump(CurDAG);\n"
>> + << " N.getNode()->dump(CurDAG);\n"
>> << " } else {\n"
>> << " unsigned iid = cast<ConstantSDNode>(N.getOperand("
>> "N.getOperand(0).getValueType() == MVT::Other))-
>>> getValue();\n"
>>
>>
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