[llvm-commits] [llvm] r55531 - /llvm/trunk/lib/Target/ARM/ARMInstrFormats.td

[Evan Cheng]

Author: evancheng
Date: Fri Aug 29 02:40:52 2008
New Revision: 55531

URL: http://llvm.org/viewvc/llvm-project?rev=55531&view=rev
Log:
addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=55531&r1=55530&r2=55531&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Aug 29 02:40:52 2008
@@ -50,7 +50,6 @@
 def VFPFrm      : Format<26>;
 
 
-
 //===----------------------------------------------------------------------===//
 
 // ARM Instruction templates.
@@ -59,6 +58,8 @@
 class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
               Format f, string cstr>
   : Instruction {
+  field bits<32> Inst;
+
   let Namespace = "ARM";
 
   bits<4> Opcode = opcod;
@@ -122,11 +123,17 @@
 class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
           string asm, list<dag> pattern>
   : I<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
-      asm, "", pattern>;
+      asm, "", pattern> {
+  let Inst{5-6}  = 0;
+  let Inst{7-10} = opcod;
+}
 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
            string asm, list<dag> pattern>
   : sI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
-       asm, "", pattern>;
+       asm, "", pattern> {
+  let Inst{5-6}  = 0;
+  let Inst{7-10} = opcod;
+}
 class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
           string asm, list<dag> pattern>
   : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,