[llvm-commits] [llvm] r55480 - /llvm/trunk/utils/TableGen/FastISelEmitter.cpp

[Owen Anderson]

Author: resistor
Date: Thu Aug 28 13:06:12 2008
New Revision: 55480

URL: http://llvm.org/viewvc/llvm-project?rev=55480&view=rev
Log:
Add support for fast-isel of opcodes that require use of extract_subreg.  Because of how extract_subreg is treated, it requires special case handling.

Modified:
    llvm/trunk/utils/TableGen/FastISelEmitter.cpp

Modified: llvm/trunk/utils/TableGen/FastISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FastISelEmitter.cpp?rev=55480&r1=55479&r2=55480&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/FastISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/FastISelEmitter.cpp Thu Aug 28 13:06:12 2008
@@ -172,6 +172,7 @@
 struct InstructionMemo {
   std::string Name;
   const CodeGenRegisterClass *RC;
+  unsigned char SubRegNo;
 };
 
 class FastISelMap {
@@ -235,12 +236,19 @@
 
     // For now, ignore instructions where the first operand is not an
     // output register.
-    Record *Op0Rec = II.OperandList[0].Rec;
-    if (!Op0Rec->isSubClassOf("RegisterClass"))
-      continue;
-    const CodeGenRegisterClass *DstRC = &Target.getRegisterClass(Op0Rec);
-    if (!DstRC)
-      continue;
+    const CodeGenRegisterClass *DstRC = 0;
+    unsigned SubRegNo = ~0;
+    if (Op->getName() != "EXTRACT_SUBREG") {
+      Record *Op0Rec = II.OperandList[0].Rec;
+      if (!Op0Rec->isSubClassOf("RegisterClass"))
+        continue;
+      DstRC = &Target.getRegisterClass(Op0Rec);
+      if (!DstRC)
+        continue;
+    } else {
+      SubRegNo = static_cast<IntInit*>(
+                 Dst->getChild(1)->getLeafValue())->getValue();
+    }
 
     // Inspect the pattern.
     TreePatternNode *InstPatNode = Pattern.getSrcPattern();
@@ -274,7 +282,8 @@
     // Ok, we found a pattern that we can handle. Remember it.
     InstructionMemo Memo = {
       Pattern.getDstPattern()->getOperator()->getName(),
-      DstRC
+      DstRC,
+      SubRegNo
     };
     assert(!SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck) &&
            "Duplicate pattern!");
@@ -410,13 +419,19 @@
                 HasPred = true;
               }
               OS << "  return FastEmitInst_";
-              Operands.PrintManglingSuffix(OS);
-              OS << "(" << InstNS << Memo.Name << ", ";
-              OS << InstNS << Memo.RC->getName() << "RegisterClass";
-              if (!Operands.empty())
-                OS << ", ";
-              Operands.PrintArguments(OS);
-              OS << ");\n";
+              if (Memo.SubRegNo == (unsigned char)~0) {
+                Operands.PrintManglingSuffix(OS);
+                OS << "(" << InstNS << Memo.Name << ", ";
+                OS << InstNS << Memo.RC->getName() << "RegisterClass";
+                if (!Operands.empty())
+                  OS << ", ";
+                Operands.PrintArguments(OS);
+                OS << ");\n";
+              } else {
+                OS << "extractsubreg(Op0, ";
+                OS << (unsigned)Memo.SubRegNo;
+                OS << ");\n";
+              }
             }
             // Return 0 if none of the predicates were satisfied.
             if (HasPred)
@@ -482,13 +497,20 @@
               HasPred = true;
             }
             OS << "  return FastEmitInst_";
-            Operands.PrintManglingSuffix(OS);
-            OS << "(" << InstNS << Memo.Name << ", ";
-            OS << InstNS << Memo.RC->getName() << "RegisterClass";
-            if (!Operands.empty())
-              OS << ", ";
-            Operands.PrintArguments(OS);
-            OS << ");\n";
+            
+            if (Memo.SubRegNo == (unsigned char)~0) {
+              Operands.PrintManglingSuffix(OS);
+              OS << "(" << InstNS << Memo.Name << ", ";
+              OS << InstNS << Memo.RC->getName() << "RegisterClass";
+              if (!Operands.empty())
+                OS << ", ";
+              Operands.PrintArguments(OS);
+              OS << ");\n";
+            } else {
+              OS << "extractsubreg(Op0, ";
+              OS << (unsigned)Memo.SubRegNo;
+              OS << ");\n";
+            }
           }
           
           // Return 0 if none of the predicates were satisfied.