[llvm-commits] [llvm] r55375 - in /llvm/trunk: include/llvm/Target/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/IA64/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/
Owen Anderson
resistor at mac.com
Tue Aug 26 11:03:31 PDT 2008
Author: resistor
Date: Tue Aug 26 13:03:31 2008
New Revision: 55375
URL: http://llvm.org/viewvc/llvm-project?rev=55375&view=rev
Log:
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested
was inserted or not. This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.
Modified:
llvm/trunk/include/llvm/Target/TargetInstrInfo.h
llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
llvm/trunk/lib/Target/ARM/ARMInstrInfo.h
llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp
llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h
llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp
llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h
llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp
llvm/trunk/lib/Target/IA64/IA64InstrInfo.h
llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
llvm/trunk/lib/Target/Mips/MipsInstrInfo.h
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h
llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp
llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/lib/Target/X86/X86InstrInfo.h
Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=55375&r1=55374&r2=55375&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Tue Aug 26 13:03:31 2008
@@ -221,7 +221,7 @@
}
/// copyRegToReg - Add a copy between a pair of registers
- virtual void copyRegToReg(MachineBasicBlock &MBB,
+ virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55375&r1=55374&r2=55375&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Tue Aug 26 13:03:31 2008
@@ -250,9 +250,6 @@
!TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
// Unhandled type. Halt "fast" selection and bail.
return I;
- if (!TLI.isConvertLegal(SrcVT, DstVT))
- // Illegal conversion. Halt "fast" selection and bail.
- return I;
// Otherwise, insert a register-to-register copy.
TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
@@ -264,9 +261,12 @@
// Unhandled operand. Halt "fast" selection and bail.
return false;
- TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Op0, DstClass, SrcClass);
- ValueMap[I] = ResultReg;
+ bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
+ Op0, DstClass, SrcClass);
+ if (!InsertedCopy)
+ return I;
+ ValueMap[I] = ResultReg;
break;
} else
// TODO: Casting a non-integral constant?
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=55375&r1=55374&r2=55375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Tue Aug 26 13:03:31 2008
@@ -459,14 +459,14 @@
return 2;
}
-void ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
+bool ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const {
if (DestRC != SrcRC) {
- cerr << "Not yet supported!";
- abort();
+ // Not yet supported!
+ return false;
}
if (DestRC == ARM::GPRRegisterClass) {
@@ -484,7 +484,9 @@
AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYD), DestReg)
.addReg(SrcReg));
else
- abort();
+ return false;
+
+ return true;
}
static const MachineInstrBuilder &ARMInstrAddOperand(MachineInstrBuilder &MIB,
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.h?rev=55375&r1=55374&r2=55375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.h Tue Aug 26 13:03:31 2008
@@ -163,7 +163,7 @@
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const;
- virtual void copyRegToReg(MachineBasicBlock &MBB,
+ virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=55375&r1=55374&r2=55375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp Tue Aug 26 13:03:31 2008
@@ -133,15 +133,15 @@
return 2;
}
-void AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
+bool AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const {
//cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
if (DestRC != SrcRC) {
- cerr << "Not yet supported!";
- abort();
+ // Not yet supported!
+ return false;
}
if (DestRC == Alpha::GPRCRegisterClass) {
@@ -151,9 +151,11 @@
} else if (DestRC == Alpha::F8RCRegisterClass) {
BuildMI(MBB, MI, get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg);
} else {
- cerr << "Attempt to copy register that is not GPR or FPR";
- abort();
+ // Attempt to copy register that is not GPR or FPR
+ return false;
}
+
+ return true;
}
void
Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h?rev=55375&r1=55374&r2=55375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h Tue Aug 26 13:03:31 2008
@@ -42,7 +42,7 @@
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const;
- virtual void copyRegToReg(MachineBasicBlock &MBB,
+ virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=55375&r1=55374&r2=55375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Tue Aug 26 13:03:31 2008
@@ -180,7 +180,7 @@
return 0;
}
-void SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
+bool SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
@@ -218,9 +218,11 @@
BuildMI(MBB, MI, get(SPU::ORv4i32), DestReg).addReg(SrcReg)
.addReg(SrcReg);
} else {
- cerr << "Attempt to copy unknown/unsupported register class!\n";
- abort();
+ // Attempt to copy unknown/unsupported register class!
+ return false;
}
+
+ return true;
}
void
Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h?rev=55375&r1=55374&r2=55375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h Tue Aug 26 13:03:31 2008
@@ -46,7 +46,7 @@
unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
- virtual void copyRegToReg(MachineBasicBlock &MBB,
+ virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
Modified: llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp?rev=55375&r1=55374&r2=55375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp Tue Aug 26 13:03:31 2008
@@ -57,14 +57,14 @@
return 1;
}
-void IA64InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
+bool IA64InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const {
if (DestRC != SrcRC) {
- cerr << "Not yet supported!";
- abort();
+ // Not yet supported!
+ return false;
}
if(DestRC == IA64::PRRegisterClass ) // if a bool, we use pseudocode
@@ -73,6 +73,8 @@
.addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
else // otherwise, MOV works (for both gen. regs and FP regs)
BuildMI(MBB, MI, get(IA64::MOV), DestReg).addReg(SrcReg);
+
+ return true;
}
void IA64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
Modified: llvm/trunk/lib/Target/IA64/IA64InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64InstrInfo.h?rev=55375&r1=55374&r2=55375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64InstrInfo.h (original)
+++ llvm/trunk/lib/Target/IA64/IA64InstrInfo.h Tue Aug 26 13:03:31 2008
@@ -40,7 +40,7 @@
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const;
- virtual void copyRegToReg(MachineBasicBlock &MBB,
+ virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=55375&r1=55374&r2=55375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Tue Aug 26 13:03:31 2008
@@ -118,7 +118,7 @@
BuildMI(MBB, MI, get(Mips::NOP));
}
-void MipsInstrInfo::
+bool MipsInstrInfo::
copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
@@ -141,10 +141,10 @@
BuildMI(MBB, I, get(Mips::MTC1A), DestReg).addReg(SrcReg);
else if ((SrcRC == Mips::CCRRegisterClass) &&
(SrcReg == Mips::FCR31))
- return; // This register is used implicitly, no copy needed.
+ return true; // This register is used implicitly, no copy needed.
else if ((DestRC == Mips::CCRRegisterClass) &&
(DestReg == Mips::FCR31))
- return; // This register is used implicitly, no copy needed.
+ return true; // This register is used implicitly, no copy needed.
else if ((DestRC == Mips::HILORegisterClass) &&
(SrcRC == Mips::CPURegsRegisterClass)) {
unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO;
@@ -154,9 +154,10 @@
unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
BuildMI(MBB, I, get(Opc), DestReg);
} else
- assert (0 && "DestRC != SrcRC, Can't copy this register");
+ // DestRC != SrcRC, Can't copy this register
+ return false;
- return;
+ return true;
}
if (DestRC == Mips::CPURegsRegisterClass)
@@ -169,7 +170,10 @@
else if (DestRC == Mips::AFGR64RegisterClass)
BuildMI(MBB, I, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
else
- assert (0 && "Can't copy this register");
+ // Can't copy this register
+ return false;
+
+ return true;
}
void MipsInstrInfo::
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.h?rev=55375&r1=55374&r2=55375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.h Tue Aug 26 13:03:31 2008
@@ -169,7 +169,7 @@
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const;
- virtual void copyRegToReg(MachineBasicBlock &MBB,
+ virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=55375&r1=55374&r2=55375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Tue Aug 26 13:03:31 2008
@@ -315,14 +315,14 @@
return 2;
}
-void PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
+bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const {
if (DestRC != SrcRC) {
- cerr << "Not yet supported!";
- abort();
+ // Not yet supported!
+ return false;
}
if (DestRC == PPC::GPRCRegisterClass) {
@@ -340,9 +340,11 @@
} else if (DestRC == PPC::CRBITRCRegisterClass) {
BuildMI(MBB, MI, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
} else {
- cerr << "Attempt to copy register that is not GPR or FPR";
- abort();
+ // Attempt to copy register that is not GPR or FPR
+ return false;
}
+
+ return true;
}
bool
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h?rev=55375&r1=55374&r2=55375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h Tue Aug 26 13:03:31 2008
@@ -112,7 +112,7 @@
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const;
- virtual void copyRegToReg(MachineBasicBlock &MBB,
+ virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp?rev=55375&r1=55374&r2=55375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp Tue Aug 26 13:03:31 2008
@@ -109,14 +109,14 @@
return 1;
}
-void SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
+bool SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const {
if (DestRC != SrcRC) {
- cerr << "Not yet supported!";
- abort();
+ // Not yet supported!
+ return false;
}
if (DestRC == SP::IntRegsRegisterClass)
@@ -127,7 +127,10 @@
BuildMI(MBB, I, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
.addReg(SrcReg);
else
- assert (0 && "Can't copy this register");
+ // Can't copy this register
+ return false;
+
+ return true;
}
void SparcInstrInfo::
Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h?rev=55375&r1=55374&r2=55375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h Tue Aug 26 13:03:31 2008
@@ -68,7 +68,7 @@
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const;
- virtual void copyRegToReg(MachineBasicBlock &MBB,
+ virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=55375&r1=55374&r2=55375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Aug 26 13:03:31 2008
@@ -1592,7 +1592,7 @@
return 2;
}
-void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
+bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
@@ -1626,11 +1626,10 @@
} else if (DestRC == &X86::VR64RegClass) {
Opc = X86::MMX_MOVQ64rr;
} else {
- assert(0 && "Unknown regclass");
- abort();
+ return false;
}
BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg);
- return;
+ return true;
}
// Moving EFLAGS to / from another register requires a push and a pop.
@@ -1639,30 +1638,31 @@
if (DestRC == &X86::GR64RegClass) {
BuildMI(MBB, MI, get(X86::PUSHFQ));
BuildMI(MBB, MI, get(X86::POP64r), DestReg);
- return;
+ return true;
} else if (DestRC == &X86::GR32RegClass) {
BuildMI(MBB, MI, get(X86::PUSHFD));
BuildMI(MBB, MI, get(X86::POP32r), DestReg);
- return;
+ return true;
}
} else if (DestRC == &X86::CCRRegClass) {
assert(DestReg == X86::EFLAGS);
if (SrcRC == &X86::GR64RegClass) {
BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg);
BuildMI(MBB, MI, get(X86::POPFQ));
- return;
+ return true;
} else if (SrcRC == &X86::GR32RegClass) {
BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg);
BuildMI(MBB, MI, get(X86::POPFD));
- return;
+ return true;
}
}
// Moving from ST(0) turns into FpGET_ST0_32 etc.
if (SrcRC == &X86::RSTRegClass) {
// Copying from ST(0)/ST(1).
- assert((SrcReg == X86::ST0 || SrcReg == X86::ST1) &&
- "Can only copy from ST(0)/ST(1) right now");
+ if (SrcReg != X86::ST0 && SrcReg != X86::ST1)
+ // Can only copy from ST(0)/ST(1) right now
+ return false;
bool isST0 = SrcReg == X86::ST0;
unsigned Opc;
if (DestRC == &X86::RFP32RegClass)
@@ -1674,13 +1674,15 @@
Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
}
BuildMI(MBB, MI, get(Opc), DestReg);
- return;
+ return true;
}
// Moving to ST(0) turns into FpSET_ST0_32 etc.
if (DestRC == &X86::RSTRegClass) {
// Copying to ST(0). FIXME: handle ST(1) also
- assert(DestReg == X86::ST0 && "Can only copy to TOS right now");
+ if (DestReg != X86::ST0)
+ // Can only copy to TOS right now
+ return false;
unsigned Opc;
if (SrcRC == &X86::RFP32RegClass)
Opc = X86::FpSET_ST0_32;
@@ -1691,11 +1693,11 @@
Opc = X86::FpSET_ST0_80;
}
BuildMI(MBB, MI, get(Opc)).addReg(SrcReg);
- return;
+ return true;
}
- assert(0 && "Not yet supported!");
- abort();
+ // Not yet supported!
+ return false;
}
static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=55375&r1=55374&r2=55375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Tue Aug 26 13:03:31 2008
@@ -311,7 +311,7 @@
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const;
- virtual void copyRegToReg(MachineBasicBlock &MBB,
+ virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
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