[llvm-commits] [llvm] r55325 - in /llvm/trunk: include/llvm/CodeGen/FastISel.h lib/CodeGen/SelectionDAG/FastISel.cpp test/CodeGen/X86/fast-isel.ll utils/TableGen/FastISelEmitter.cpp

[Evan Cheng]

On Aug 25, 2008, at 1:20 PM, Owen Anderson wrote:

>
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55325&r1=55324&r2=55325&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Mon Aug 25  
> 15:20:32 2008
> @@ -221,6 +221,22 @@
>     case Instruction::PHI:
>       // PHI nodes are already emitted.
>       break;
> +
> +    case Instruction::BitCast:
> +      // BitCast consists of either an immediate to register move
> +      // or a register to register move.
> +      if (ConstantInt* CI = dyn_cast<ConstantInt>(I- 
> >getOperand(0))) {
> +        if (I->getType()->isInteger()) {
> +          MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/ 
> false);
> +          ValueMap[I] = FastEmit_i(VT.getSimpleVT(), ISD::Constant,
> +                                   CI->getZExtValue());
> +          break;
> +        } else
> +          // TODO: Support vector and fp constants.
> +          return I;
> +      } else
> +        // TODO: Support non-constant bitcasts.
> +        return I;

Stylistic nitpick. If you invert the if conditions, you can eliminate  
nesting:

ConstantInt *CI = dyn_cast<>...
if (!CI)
   return I;
if (!I->getType()->isInteger())
   return I;

>
>
>     default:
>       // Unhandled instruction. Halt "fast" selection and bail.
> @@ -256,7 +272,8 @@
>   return 0;
> }
>
> -unsigned FastISel::FastEmit_i(MVT::SimpleValueType, uint64_t / 
> *Imm*/) {
> +unsigned FastISel::FastEmit_i(MVT::SimpleValueType, ISD::NodeType,
> +                              uint64_t /*Imm*/) {
>   return 0;
> }
>
> @@ -284,7 +301,7 @@
>     ResultReg = FastEmit_ri(VT, Opcode, Op0, Imm);
>   if (ResultReg != 0)
>     return ResultReg;
> -  unsigned MaterialReg = FastEmit_i(ImmType, Imm);
> +  unsigned MaterialReg = FastEmit_i(ImmType, ISD::Constant, Imm);

If NodeType is not yet used. Please add an assert.

>
>   if (MaterialReg == 0)
>     return 0;
>   return FastEmit_rr(VT, Opcode, Op0, MaterialReg);
> @@ -342,3 +359,13 @@
>   BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
>   return ResultReg;
> }
> +
> +unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
> +                                  const TargetRegisterClass *RC,
> +                                  uint64_t Imm) {
> +  unsigned ResultReg = createResultReg(RC);
> +  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
> +
> +  BuildMI(MBB, II, ResultReg).addImm(Imm);
> +  return ResultReg;
> +}

>
> \ No newline at end of file

Plz fix this.

Thanks,

Evan

>
>
> Modified: llvm/trunk/test/CodeGen/X86/fast-isel.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel.ll?rev=55325&r1=55324&r2=55325&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/fast-isel.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/fast-isel.ll Mon Aug 25 15:20:32 2008
> @@ -41,3 +41,8 @@
>   ret double %t2
> }
>
> +define i32 @cast(){
> +entry:
> +	%tmp2 = bitcast i32 0 to i32
> +	ret i32 %tmp2
> +}
>
> Modified: llvm/trunk/utils/TableGen/FastISelEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FastISelEmitter.cpp?rev=55325&r1=55324&r2=55325&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/utils/TableGen/FastISelEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/FastISelEmitter.cpp Mon Aug 25  
> 15:20:32 2008
> @@ -64,6 +64,12 @@
>                   const CodeGenTarget &Target,
>                   MVT::SimpleValueType VT,
>                   const CodeGenRegisterClass *DstRC) {
> +    if (!InstPatNode->isLeaf() &&
> +        InstPatNode->getOperator()->getName() == "imm") {
> +      Operands.push_back("i");
> +      return true;
> +    }
> +
>     for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; + 
> +i) {
>       TreePatternNode *Op = InstPatNode->getChild(i);
>       // For now, filter out any operand with a predicate.
> @@ -219,9 +225,6 @@
>     // an Operand or an immediate, like MOV32ri.
>     if (InstPatOp->isSubClassOf("Operand"))
>       continue;
> -    if (InstPatOp->getName() == "imm" ||
> -        InstPatOp->getName() == "fpimm")
> -      continue;
>
>     // For now, filter out any instructions with predicates.
>     if (!InstPatNode->getPredicateFn().empty())
>
>
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