[llvm-commits] [llvm] r55336 - in /llvm/trunk/lib/Target/PowerPC: PPCISelLowering.cpp PPCISelLowering.h PPCInstr64Bit.td PPCInstrInfo.td

Dale Johannesen dalej at apple.com
Mon Aug 25 14:09:52 PDT 2008


Author: johannes
Date: Mon Aug 25 16:09:52 2008
New Revision: 55336

URL: http://llvm.org/viewvc/llvm-project?rev=55336&view=rev
Log:
Remove PPC-specific lowering for atomics; the
generic stuff works fine.

Mark rewritten cmp-and-swap as not using CR1.


Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
    llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
    llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=55336&r1=55335&r2=55336&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Aug 25 16:09:52 2008
@@ -203,15 +203,6 @@
   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Custom);
   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64  , Custom);
 
-  setOperationAction(ISD::ATOMIC_LOAD_ADD   , MVT::i32  , Custom);
-  setOperationAction(ISD::ATOMIC_CMP_SWAP   , MVT::i32  , Custom);
-  setOperationAction(ISD::ATOMIC_SWAP       , MVT::i32  , Custom);
-  if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
-    setOperationAction(ISD::ATOMIC_LOAD_ADD , MVT::i64  , Custom);
-    setOperationAction(ISD::ATOMIC_CMP_SWAP , MVT::i64  , Custom);
-    setOperationAction(ISD::ATOMIC_SWAP     , MVT::i64  , Custom);
-  }
-
   // We want to custom lower some of our intrinsics.
   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
   
@@ -405,9 +396,6 @@
   case PPCISD::VCMPo:           return "PPCISD::VCMPo";
   case PPCISD::LBRX:            return "PPCISD::LBRX";
   case PPCISD::STBRX:           return "PPCISD::STBRX";
-  case PPCISD::ATOMIC_LOAD_ADD: return "PPCISD::ATOMIC_LOAD_ADD";
-  case PPCISD::ATOMIC_CMP_SWAP: return "PPCISD::ATOMIC_CMP_SWAP";
-  case PPCISD::ATOMIC_SWAP:     return "PPCISD::ATOMIC_SWAP";
   case PPCISD::LARX:            return "PPCISD::LARX";
   case PPCISD::STCX:            return "PPCISD::STCX";
   case PPCISD::COND_BRANCH:     return "PPCISD::COND_BRANCH";
@@ -2722,53 +2710,6 @@
   return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3);
 }
 
-SDValue PPCTargetLowering::LowerAtomicLOAD_ADD(SDValue Op, SelectionDAG &DAG) {
-  MVT VT = Op.Val->getValueType(0);
-  SDValue Chain   = Op.getOperand(0);
-  SDValue Ptr     = Op.getOperand(1);
-  SDValue Incr    = Op.getOperand(2);
-
-  SDVTList VTs = DAG.getVTList(VT, MVT::Other);
-  SDValue Ops[] = {
-    Chain,
-    Ptr,
-    Incr,
-  };
-  return DAG.getNode(PPCISD::ATOMIC_LOAD_ADD, VTs, Ops, 3);
-}
-
-SDValue PPCTargetLowering::LowerAtomicCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
-  MVT VT = Op.Val->getValueType(0);
-  SDValue Chain   = Op.getOperand(0);
-  SDValue Ptr     = Op.getOperand(1);
-  SDValue NewVal  = Op.getOperand(2);
-  SDValue OldVal  = Op.getOperand(3);
-
-  SDVTList VTs = DAG.getVTList(VT, MVT::Other);
-  SDValue Ops[] = {
-    Chain,
-    Ptr,
-    OldVal,
-    NewVal,
-  };
-  return DAG.getNode(PPCISD::ATOMIC_CMP_SWAP, VTs, Ops, 4);
-}
-
-SDValue PPCTargetLowering::LowerAtomicSWAP(SDValue Op, SelectionDAG &DAG) {
-  MVT VT = Op.Val->getValueType(0);
-  SDValue Chain   = Op.getOperand(0);
-  SDValue Ptr     = Op.getOperand(1);
-  SDValue NewVal  = Op.getOperand(2);
-
-  SDVTList VTs = DAG.getVTList(VT, MVT::Other);
-  SDValue Ops[] = {
-    Chain,
-    Ptr,
-    NewVal,
-  };
-  return DAG.getNode(PPCISD::ATOMIC_SWAP, VTs, Ops, 3);
-}
-
 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
 /// possible.
 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
@@ -3876,10 +3817,6 @@
   case ISD::DYNAMIC_STACKALLOC:
     return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
 
-  case ISD::ATOMIC_LOAD_ADD:    return LowerAtomicLOAD_ADD(Op, DAG);
-  case ISD::ATOMIC_CMP_SWAP:    return LowerAtomicCMP_SWAP(Op, DAG);
-  case ISD::ATOMIC_SWAP:        return LowerAtomicSWAP(Op, DAG);
-    
   case ISD::SELECT_CC:          return LowerSELECT_CC(Op, DAG);
   case ISD::FP_TO_SINT:         return LowerFP_TO_SINT(Op, DAG);
   case ISD::SINT_TO_FP:         return LowerSINT_TO_FP(Op, DAG);

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=55336&r1=55335&r2=55336&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Mon Aug 25 16:09:52 2008
@@ -152,11 +152,6 @@
       /// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR.
       MTFSF,
 
-      /// ATOMIC_LOAD_ADD, ATOMIC_CMP_SWAP, ATOMIC_SWAP - These
-      /// correspond to the llvm.atomic.load.add, llvm.atomic.cmp.swap
-      /// and llvm.atomic.swap intrinsics.
-      ATOMIC_LOAD_ADD, ATOMIC_CMP_SWAP, ATOMIC_SWAP,
-
       /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
       /// reserve indexed. This is used to implement atomic operations.
       LARX,
@@ -363,9 +358,6 @@
     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
                                       const PPCSubtarget &Subtarget);
     SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
-    SDValue LowerAtomicLOAD_ADD(SDValue Op, SelectionDAG &DAG);
-    SDValue LowerAtomicCMP_SWAP(SDValue Op, SelectionDAG &DAG);
-    SDValue LowerAtomicSWAP(SDValue Op, SelectionDAG &DAG);
     SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG);
     SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG);
     SDValue LowerFP_ROUND_INREG(SDValue Op, SelectionDAG &DAG);

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=55336&r1=55335&r2=55336&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Mon Aug 25 16:09:52 2008
@@ -122,18 +122,16 @@
     def ATOMIC_LOAD_ADD_I64 : Pseudo<
       (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr),
       "${:comment} ATOMIC_LOAD_ADD_I64 PSEUDO!",
-      [(set G8RC:$dst, (PPCatomic_load_add xoaddr:$ptr, G8RC:$incr))]>;
-    def ATOMIC_SWAP_I64 : Pseudo<
-      (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new),
-      "${:comment} ATOMIC_SWAP_I64 PSEUDO!",
-      [(set G8RC:$dst, (PPCatomic_swap xoaddr:$ptr, G8RC:$new))]>;
-  }
-  let Uses = [CR0, CR1] in {
+      [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>;
     def ATOMIC_CMP_SWAP_I64 : Pseudo<
       (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new),
       "${:comment} ATOMIC_CMP_SWAP_I64 PSEUDO!",
       [(set G8RC:$dst, 
-                    (PPCatomic_cmp_swap xoaddr:$ptr, G8RC:$old, G8RC:$new))]>;
+                    (atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>;
+    def ATOMIC_SWAP_I64 : Pseudo<
+      (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new),
+      "${:comment} ATOMIC_SWAP_I64 PSEUDO!",
+      [(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>;
   }
 }
 

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=55336&r1=55335&r2=55336&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Mon Aug 25 16:09:52 2008
@@ -42,16 +42,6 @@
   SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
 ]>;
 
-def SDT_PPCatomic_load_add : SDTypeProfile<1, 2, [
-  SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisInt<2>
-]>;
-def SDT_PPCatomic_cmp_swap : SDTypeProfile<1, 3, [
-  SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisInt<2>, SDTCisInt<3>
-]>;
-def SDT_PPCatomic_swap : SDTypeProfile<1, 2, [
-  SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisInt<2>
-]>;
-
 def SDT_PPClarx : SDTypeProfile<1, 1, [
   SDTCisInt<0>, SDTCisPtrTy<1>
 ]>;
@@ -149,17 +139,6 @@
 def PPCstbrx      : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
                            [SDNPHasChain, SDNPMayStore]>;
 
-// Atomic operations
-def PPCatomic_load_add : SDNode<"PPCISD::ATOMIC_LOAD_ADD",
-                                SDT_PPCatomic_load_add,
-                                [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
-def PPCatomic_cmp_swap : SDNode<"PPCISD::ATOMIC_CMP_SWAP",
-                                SDT_PPCatomic_cmp_swap,
-                                [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
-def PPCatomic_swap : SDNode<"PPCISD::ATOMIC_SWAP",
-                            SDT_PPCatomic_swap,
-                            [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
-
 // Instructions to support atomic operations
 def PPClarx      : SDNode<"PPCISD::LARX", SDT_PPClarx,
                           [SDNPHasChain, SDNPMayLoad]>;
@@ -552,18 +531,16 @@
     def ATOMIC_LOAD_ADD_I32 : Pseudo<
       (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
       "${:comment} ATOMIC_LOAD_ADD_I32 PSEUDO!",
-      [(set GPRC:$dst, (PPCatomic_load_add xoaddr:$ptr, GPRC:$incr))]>;
-    def ATOMIC_SWAP_I32 : Pseudo<
-      (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new),
-      "${:comment} ATOMIC_SWAP_I32 PSEUDO!",
-      [(set GPRC:$dst, (PPCatomic_swap xoaddr:$ptr, GPRC:$new))]>;
-  }
-  let Uses = [CR0, CR1] in {
+      [(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>;
     def ATOMIC_CMP_SWAP_I32 : Pseudo<
       (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new),
       "${:comment} ATOMIC_CMP_SWAP_I32 PSEUDO!",
       [(set GPRC:$dst, 
-                    (PPCatomic_cmp_swap xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
+                    (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
+    def ATOMIC_SWAP_I32 : Pseudo<
+      (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new),
+      "${:comment} ATOMIC_SWAP_I32 PSEUDO!",
+      [(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>;
   }
 }
 





More information about the llvm-commits mailing list