[llvm-commits] [llvm] r55018 - in /llvm/trunk: lib/Target/TargetSelectionDAG.td lib/Target/X86/X86Instr64bit.td lib/Target/X86/X86InstrInfo.td test/CodeGen/X86/2008-08-19-SubAndFetch.ll
Bill Wendling
isanbard at gmail.com
Tue Aug 19 16:09:19 PDT 2008
Author: void
Date: Tue Aug 19 18:09:18 2008
New Revision: 55018
URL: http://llvm.org/viewvc/llvm-project?rev=55018&view=rev
Log:
Add support for the __sync_sub_and_fetch atomics and friends for X86. The code
was already present, but not hooked up to anything.
Added:
llvm/trunk/test/CodeGen/X86/2008-08-19-SubAndFetch.ll
Modified:
llvm/trunk/lib/Target/TargetSelectionDAG.td
llvm/trunk/lib/Target/X86/X86Instr64bit.td
llvm/trunk/lib/Target/X86/X86InstrInfo.td
Modified: llvm/trunk/lib/Target/TargetSelectionDAG.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetSelectionDAG.td?rev=55018&r1=55017&r2=55018&view=diff
==============================================================================
--- llvm/trunk/lib/Target/TargetSelectionDAG.td (original)
+++ llvm/trunk/lib/Target/TargetSelectionDAG.td Tue Aug 19 18:09:18 2008
@@ -358,10 +358,10 @@
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , STDAtomic2,
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", STDAtomic2,
- [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , STDAtomic2,
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", STDAtomic2,
+ [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , STDAtomic2,
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , STDAtomic2,
@@ -815,6 +815,32 @@
return false;
}]>;
+def atomic_load_sub_8 : PatFrag<(ops node:$ptr, node:$dec),
+ (atomic_load_sub node:$ptr, node:$dec), [{
+ if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
+ return V->getValueType(0) == MVT::i8;
+ return false;
+}]>;
+def atomic_load_sub_16 : PatFrag<(ops node:$ptr, node:$dec),
+ (atomic_load_sub node:$ptr, node:$dec), [{
+ if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
+ return V->getValueType(0) == MVT::i16;
+ return false;
+}]>;
+def atomic_load_sub_32 : PatFrag<(ops node:$ptr, node:$dec),
+ (atomic_load_sub node:$ptr, node:$dec), [{
+ if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
+ return V->getValueType(0) == MVT::i32;
+ return false;
+}]>;
+def atomic_load_sub_64 : PatFrag<(ops node:$ptr, node:$dec),
+ (atomic_load_sub node:$ptr, node:$dec), [{
+ if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
+ return V->getValueType(0) == MVT::i64;
+ return false;
+}]>;
+
+
def atomic_swap_8 : PatFrag<(ops node:$ptr, node:$inc),
(atomic_swap node:$ptr, node:$inc), [{
if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
@@ -841,7 +867,6 @@
}]>;
-
// setcc convenience fragments.
def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
(setcc node:$lhs, node:$rhs, SETOEQ)>;
Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=55018&r1=55017&r2=55018&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
+++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Tue Aug 19 18:09:18 2008
@@ -1133,18 +1133,25 @@
let Defs = [RAX, EFLAGS], Uses = [RAX] in {
def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
- "lock\n\tcmpxchgq $swap,$ptr",
+ "lock\n\tcmpxchgq\t$swap,$ptr",
[(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
}
let Constraints = "$val = $dst" in {
let Defs = [EFLAGS] in
def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
- "lock\n\txadd $val, $ptr",
+ "lock\n\txadd\t$val, $ptr",
[(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
TB, LOCK;
+
+let Defs = [EFLAGS] in
+def LXSUB64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
+ "lock\n\txadd\t$val, $ptr",
+ [(set GR64:$dst, (atomic_load_sub_64 addr:$ptr, GR64:$val))]>,
+ TB, LOCK;
+
def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
- "xchg $val, $ptr",
+ "xchg\t$val, $ptr",
[(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
}
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=55018&r1=55017&r2=55018&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Aug 19 18:09:18 2008
@@ -2634,6 +2634,22 @@
TB, LOCK;
}
+// Atomic exchange and subtract
+let Constraints = "$val = $dst", Defs = [EFLAGS] in {
+def LXSUB32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
+ "lock\n\txadd{l}\t{$val, $ptr|$ptr, $val}",
+ [(set GR32:$dst, (atomic_load_sub_32 addr:$ptr, GR32:$val))]>,
+ TB, LOCK;
+def LXSUB16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
+ "lock\n\txadd{w}\t{$val, $ptr|$ptr, $val}",
+ [(set GR16:$dst, (atomic_load_sub_16 addr:$ptr, GR16:$val))]>,
+ TB, OpSize, LOCK;
+def LXSUB8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
+ "lock\n\txadd{b}\t{$val, $ptr|$ptr, $val}",
+ [(set GR8:$dst, (atomic_load_sub_8 addr:$ptr, GR8:$val))]>,
+ TB, LOCK;
+}
+
// Atomic exchange, and, or, xor
let Constraints = "$val = $dst", Defs = [EFLAGS],
usesCustomDAGSchedInserter = 1 in {
Added: llvm/trunk/test/CodeGen/X86/2008-08-19-SubAndFetch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-08-19-SubAndFetch.ll?rev=55018&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-08-19-SubAndFetch.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2008-08-19-SubAndFetch.ll Tue Aug 19 18:09:18 2008
@@ -0,0 +1,11 @@
+; RUN: llvm-as < %s | llc -march=x86-64 | grep xadd
+
+ at var = external global i64 ; <i64*> [#uses=1]
+
+define i32 @main() nounwind {
+entry:
+ tail call i64 @llvm.atomic.load.sub.i64.p0i64( i64* @var, i64 1 ) ; <i64>:0 [#uses=0]
+ unreachable
+}
+
+declare i64 @llvm.atomic.load.sub.i64.p0i64(i64*, i64) nounwind
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