[llvm-commits] [llvm] r54968 - /llvm/trunk/lib/CodeGen/VirtRegMap.cpp

[Owen Anderson]

Author: resistor
Date: Mon Aug 18 20:05:33 2008
New Revision: 54968

URL: http://llvm.org/viewvc/llvm-project?rev=54968&view=rev
Log:
Make SimpleSpiller respect subregister indices.

Modified:
    llvm/trunk/lib/CodeGen/VirtRegMap.cpp

Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=54968&r1=54967&r2=54968&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original)
+++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Mon Aug 18 20:05:33 2008
@@ -241,6 +241,7 @@
   DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
   const TargetMachine &TM = MF.getTarget();
   const TargetInstrInfo &TII = *TM.getInstrInfo();
+  const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
   
 
   // LoadedRegs - Keep track of which vregs are loaded, so that we only load
@@ -261,7 +262,9 @@
         if (MO.isRegister() && MO.getReg()) {
           if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
             unsigned VirtReg = MO.getReg();
+            unsigned SubIdx = MO.getSubReg();
             unsigned PhysReg = VRM.getPhys(VirtReg);
+            unsigned RReg = SubIdx ? TRI.getSubReg(PhysReg, SubIdx) : PhysReg;
             if (!VRM.isAssignedReg(VirtReg)) {
               int StackSlot = VRM.getStackSlot(VirtReg);
               const TargetRegisterClass* RC =
@@ -286,8 +289,8 @@
                 ++NumStores;
               }
             }
-            MF.getRegInfo().setPhysRegUsed(PhysReg);
-            MI.getOperand(i).setReg(PhysReg);
+            MF.getRegInfo().setPhysRegUsed(RReg);
+            MI.getOperand(i).setReg(RReg);
           } else {
             MF.getRegInfo().setPhysRegUsed(MO.getReg());
           }