[llvm-commits] [llvm] r54767 - in /llvm/trunk: lib/Analysis/ValueTracking.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/Transforms/Scalar/InstructionCombining.cpp test/Transforms/InstCombine/srem1.ll

[Dan Gohman]

Author: djg
Date: Wed Aug 13 18:12:35 2008
New Revision: 54767

URL: http://llvm.org/viewvc/llvm-project?rev=54767&view=rev
Log:
Fix a bogus srem rule - a negative value srem'd by a power-of-2
can have a non-negative result; for example, -16%16 is 0. Also,
clarify the related comments. This fixes PR2670.

Added:
    llvm/trunk/test/Transforms/InstCombine/srem1.ll
Modified:
    llvm/trunk/lib/Analysis/ValueTracking.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp

Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=54767&r1=54766&r2=54767&view=diff

==============================================================================
--- llvm/trunk/lib/Analysis/ValueTracking.cpp (original)
+++ llvm/trunk/lib/Analysis/ValueTracking.cpp Wed Aug 13 18:12:35 2008
@@ -369,15 +369,13 @@
         ComputeMaskedBits(I->getOperand(0), Mask2, KnownZero2, KnownOne2, TD, 
                           Depth+1);
 
-        // The sign of a remainder is equal to the sign of the first
-        // operand (zero being positive).
+        // If the sign bit of the first operand is zero, the sign bit of
+        // the result is zero. If the first operand has no one bits below
+        // the second operand's single 1 bit, its sign will be zero.
         if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits))
           KnownZero2 |= ~LowBits;
-        else if (KnownOne2[BitWidth-1])
-          KnownOne2 |= ~LowBits;
 
         KnownZero |= KnownZero2 & Mask;
-        KnownOne |= KnownOne2 & Mask;
 
         assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 
       }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=54767&r1=54766&r2=54767&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Aug 13 18:12:35 2008
@@ -1656,15 +1656,13 @@
         APInt Mask2 = LowBits | APInt::getSignBit(BitWidth);
         ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1);
 
-        // The sign of a remainder is equal to the sign of the first
-        // operand (zero being positive).
+        // If the sign bit of the first operand is zero, the sign bit of
+        // the result is zero. If the first operand has no one bits below
+        // the second operand's single 1 bit, its sign will be zero.
         if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits))
           KnownZero2 |= ~LowBits;
-        else if (KnownOne2[BitWidth-1])
-          KnownOne2 |= ~LowBits;
 
         KnownZero |= KnownZero2 & Mask;
-        KnownOne |= KnownOne2 & Mask;
 
         assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?");
       }

Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=54767&r1=54766&r2=54767&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Wed Aug 13 18:12:35 2008
@@ -1266,11 +1266,8 @@
 
         if (LHSKnownZero[BitWidth-1] || ((LHSKnownZero & LowBits) == LowBits))
           LHSKnownZero |= ~LowBits;
-        else if (LHSKnownOne[BitWidth-1])
-          LHSKnownOne |= ~LowBits;
 
         KnownZero |= LHSKnownZero & DemandedMask;
-        KnownOne |= LHSKnownOne & DemandedMask;
 
         assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 
       }

Added: llvm/trunk/test/Transforms/InstCombine/srem1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/srem1.ll?rev=54767&view=auto

==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/srem1.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/srem1.ll Wed Aug 13 18:12:35 2008
@@ -0,0 +1,18 @@
+; RUN: llvm-as < %s | opt -instcombine
+; PR2670
+
+ at g_127 = external global i32		; <i32*> [#uses=1]
+
+define i32 @func_56(i32 %p_58, i32 %p_59, i32 %p_61, i16 signext %p_62) nounwind {
+entry:
+	%call = call i32 (...)* @rshift_s_s( i32 %p_61, i32 1 )		; <i32> [#uses=1]
+	%conv = sext i32 %call to i64		; <i64> [#uses=1]
+	%or = or i64 -1734012817166602727, %conv		; <i64> [#uses=1]
+	%rem = srem i64 %or, 1		; <i64> [#uses=1]
+	%cmp = icmp eq i64 %rem, 1		; <i1> [#uses=1]
+	%cmp.ext = zext i1 %cmp to i32		; <i32> [#uses=1]
+	store i32 %cmp.ext, i32* @g_127
+	ret i32 undef
+}
+
+declare i32 @rshift_s_s(...)