[llvm-commits] [llvm] r54544 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.cpp lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/extractps.ll

[Dan Gohman]

Author: djg
Date: Fri Aug  8 13:30:21 2008
New Revision: 54544

URL: http://llvm.org/viewvc/llvm-project?rev=54544&view=rev
Log:
Add an EXTRACTPSmr pattern to match the pattern that
X86ISelLowering creates.

Added:
    llvm/trunk/test/CodeGen/X86/extractps.ll
Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=54544&r1=54543&r2=54544&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Fri Aug  8 13:30:21 2008
@@ -238,6 +238,7 @@
     { X86::DIV32r,      X86::DIV32m, 1 },
     { X86::DIV64r,      X86::DIV64m, 1 },
     { X86::DIV8r,       X86::DIV8m, 1 },
+    { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0 },
     { X86::FsMOVAPDrr,  X86::MOVSDmr, 0 },
     { X86::FsMOVAPSrr,  X86::MOVSSmr, 0 },
     { X86::IDIV16r,     X86::IDIV16m, 1 },

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=54544&r1=54543&r2=54544&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri Aug  8 13:30:21 2008
@@ -3485,6 +3485,13 @@
 
 defm EXTRACTPS   : SS41I_extractf32<0x17, "extractps">;
 
+// Also match an EXTRACTPS store when the store is done as f32 instead of i32.
+def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
+                                              imm:$src2))),
+                 addr:$dst),
+          (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
+         Requires<[HasSSE41]>;
+
 let Constraints = "$src1 = $dst" in {
   multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
     def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),

Added: llvm/trunk/test/CodeGen/X86/extractps.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/extractps.ll?rev=54544&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/extractps.ll (added)
+++ llvm/trunk/test/CodeGen/X86/extractps.ll Fri Aug  8 13:30:21 2008
@@ -0,0 +1,16 @@
+; RUN: llvm-as < %s | llc -mcpu=penryn | grep mov | count 1
+; PR2647
+
+external global float, align 16         ; <float*>:0 [#uses=2]
+
+define internal void @""() nounwind {
+        load float* @0, align 16                ; <float>:1 [#uses=1]
+        insertelement <4 x float> undef, float %1, i32 0                ; <<4 x float>>:2 [#uses=1]
+        call <4 x float> @llvm.x86.sse.rsqrt.ss( <4 x float> %2 )              ; <<4 x float>>:3 [#uses=1]
+        extractelement <4 x float> %3, i32 0            ; <float>:4 [#uses=1]
+        store float %4, float* @0, align 16
+        ret void
+}
+
+declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>) nounwind readnone
+