[llvm-commits] [llvm] r54443 - /llvm/trunk/test/CodeGen/X86/zext-inreg-1.ll

[Dan Gohman]

Author: djg
Date: Wed Aug  6 21:23:06 2008
New Revision: 54443

URL: http://llvm.org/viewvc/llvm-project?rev=54443&view=rev
Log:
Add an extra example that shouldn't get an and instruction.

Modified:
    llvm/trunk/test/CodeGen/X86/zext-inreg-1.ll

Modified: llvm/trunk/test/CodeGen/X86/zext-inreg-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/zext-inreg-1.ll?rev=54443&r1=54442&r2=54443&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/zext-inreg-1.ll (original)
+++ llvm/trunk/test/CodeGen/X86/zext-inreg-1.ll Wed Aug  6 21:23:06 2008
@@ -6,7 +6,12 @@
 ; These should use movzbl instead of 'and 255'.
 ; This related to not having ZERO_EXTEND_REG node.
 
-define i64 @h(i64 %d) nounwind  {
+define i64 @l(i64 %d) nounwind  {
+        %e = add i64 %d, 1
+        %retval = and i64 %e, 1099511627775
+        ret i64 %retval
+}
+define i64 @m(i64 %d) nounwind  {
         %e = add i64 %d, 1
         %retval = and i64 %e, 281474976710655
         ret i64 %retval