[llvm-commits] [llvm] r54147 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGNodes.h lib/Target/X86/X86Instr64bit.td lib/Target/X86/X86InstrInfo.td test/CodeGen/X86/zext-inreg-0.ll test/CodeGen/X86/zext-inreg-1.ll
Bill Wendling
isanbard at gmail.com
Mon Jul 28 15:38:37 PDT 2008
Dan,
A bootstrap build is failing with this:
/Volumes/Sandbox/Buildbot/llvm/full-llvm-gcc/llvm-gcc.obj/./gcc/xgcc
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm-gcc/llvm-gcc.obj/./gcc/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm-gcc/llvm-gcc.install/i386-apple-darwin9.4.0/bin/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm-gcc/llvm-gcc.install/i386-apple-darwin9.4.0/lib/
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm-gcc/llvm-gcc.install/i386-apple-darwin9.4.0/include
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm-gcc/llvm-gcc.install/i386-apple-darwin9.4.0/sys-include
-mmacosx-version-min=10.4 -O2 -O2 -g -O2 -DIN_GCC -W -Wall
-Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes
-Wold-style-definition -isystem ./include -fPIC -pipe -g
-DHAVE_GTHR_DEFAULT -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED -I. -I.
-I../../llvm-gcc.src/gcc -I../../llvm-gcc.src/gcc/.
-I../../llvm-gcc.src/gcc/../include -I./../intl
-I../../llvm-gcc.src/gcc/../libcpp/include
-I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/llvm.obj/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/llvm/include -DL_paritydi2
-fvisibility=hidden -DHIDE_EXPORTS -c ../../llvm-gcc.src/gcc/libgcc2.c
-o libgcc/./_paritydi2.o
{standard input}:20:bad register name `%sil'
/Volumes/Sandbox/Buildbot/llvm/full-llvm-gcc/llvm-gcc.obj/./gcc/xgcc
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm-gcc/llvm-gcc.obj/./gcc/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm-gcc/llvm-gcc.install/i386-apple-darwin9.4.0/bin/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm-gcc/llvm-gcc.install/i386-apple-darwin9.4.0/lib/
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm-gcc/llvm-gcc.install/i386-apple-darwin9.4.0/include
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm-gcc/llvm-gcc.install/i386-apple-darwin9.4.0/sys-include
-mmacosx-version-min=10.4 -O2 -O2 -g -O2 -DIN_GCC -W -Wall
-Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes
-Wold-style-definition -isystem ./include -fPIC -pipe -g
-DHAVE_GTHR_DEFAULT -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED -I. -I.
-I../../llvm-gcc.src/gcc -I../../llvm-gcc.src/gcc/.
-I../../llvm-gcc.src/gcc/../include -I./../intl
-I../../llvm-gcc.src/gcc/../libcpp/include
-I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/llvm.obj/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/llvm/include -DL_powisf2
-fvisibility=hidden -DHIDE_EXPORTS -c ../../llvm-gcc.src/gcc/libgcc2.c
-o libgcc/./_powisf2.o
make[4]: *** [libgcc/./_popcountsi2.o] Error 1
make[4]: *** Waiting for unfinished jobs....
{standard input}:20:bad register name `%sil'
{standard input}:42:bad register name `%sil'
make[4]: *** [libgcc/./_popcountdi2.o] Error 1
make[3]: *** [stmp-multilib] Error 2
make[2]: *** [all-stage1-gcc] Error 2
make[1]: *** [stage1-bubble] Error 2
make: *** [all] Error 2
-bw
On Mon, Jul 28, 2008 at 3:18 PM, Dan Gohman <gohman at apple.com> wrote:
> Author: djg
> Date: Mon Jul 28 17:18:25 2008
> New Revision: 54147
>
> URL: http://llvm.org/viewvc/llvm-project?rev=54147&view=rev
> Log:
> Add x86 isel patterns to match what would be a ZERO_EXTEND_INREG operation,
> which is represented in codegen as an 'and' operation. This matches them
> with movz instructions, instead of leaving them to be matched by and
> instructions with an immediate field.
>
> Added:
> llvm/trunk/test/CodeGen/X86/zext-inreg-0.ll
> llvm/trunk/test/CodeGen/X86/zext-inreg-1.ll
> Modified:
> llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
> llvm/trunk/lib/Target/X86/X86Instr64bit.td
> llvm/trunk/lib/Target/X86/X86InstrInfo.td
>
> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=54147&r1=54146&r2=54147&view=diff
>
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Mon Jul 28 17:18:25 2008
> @@ -377,6 +377,8 @@
> // extending the low 8 bits of a 32-bit register to fill the top 24 bits
> // with the 7th bit). The size of the smaller type is indicated by the 1th
> // operand, a ValueType node.
> + // Note that there is intentionally no corresponding ZERO_EXTEND_INREG; an
> + // AND with an appropriate constant is used instead.
> SIGN_EXTEND_INREG,
>
> /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned
>
> Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=54147&r1=54146&r2=54147&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
> +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Mon Jul 28 17:18:25 2008
> @@ -1240,6 +1240,12 @@
> (SUBREG_TO_REG (i64 0),
> (i32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)),
> x86_subreg_32bit)>;
> +// r & (2^16-1) ==> movz
> +def : Pat<(and GR64:$src, 0xffff),
> + (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
> +// r & (2^8-1) ==> movz
> +def : Pat<(and GR64:$src, 0xff),
> + (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
>
> // (shl x, 1) ==> (add x, x)
> def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=54147&r1=54146&r2=54147&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Jul 28 17:18:25 2008
> @@ -2763,6 +2763,16 @@
> // Some peepholes
> //===----------------------------------------------------------------------===//
>
> +// r & (2^16-1) ==> movz
> +def : Pat<(and GR32:$src1, 0xffff),
> + (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit)))>;
> +// r & (2^8-1) ==> movz
> +def : Pat<(and GR32:$src1, 0xff),
> + (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit)))>;
> +// r & (2^8-1) ==> movz
> +def : Pat<(and GR16:$src1, 0xff),
> + (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>;
> +
> // (shl x, 1) ==> (add x, x)
> def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
> def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
>
> Added: llvm/trunk/test/CodeGen/X86/zext-inreg-0.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/zext-inreg-0.ll?rev=54147&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/zext-inreg-0.ll (added)
> +++ llvm/trunk/test/CodeGen/X86/zext-inreg-0.ll Mon Jul 28 17:18:25 2008
> @@ -0,0 +1,62 @@
> +; RUN: llvm-as < %s | llc -march=x86 | not grep and
> +; RUN: llvm-as < %s | llc -march=x86-64 | not grep and
> +
> +; These should use movzbl instead of 'and 255'.
> +; This related to not having a ZERO_EXTEND_REG opcode.
> +
> +define i32 @a(i32 %d) nounwind {
> + %e = add i32 %d, 1
> + %retval = and i32 %e, 255
> + ret i32 %retval
> +}
> +define i32 @b(float %d) nounwind {
> + %tmp12 = fptoui float %d to i8
> + %retval = zext i8 %tmp12 to i32
> + ret i32 %retval
> +}
> +define i32 @c(i32 %d) nounwind {
> + %e = add i32 %d, 1
> + %retval = and i32 %e, 65535
> + ret i32 %retval
> +}
> +define i64 @d(i64 %d) nounwind {
> + %e = add i64 %d, 1
> + %retval = and i64 %e, 255
> + ret i64 %retval
> +}
> +define i64 @e(i64 %d) nounwind {
> + %e = add i64 %d, 1
> + %retval = and i64 %e, 65535
> + ret i64 %retval
> +}
> +define i64 @f(i64 %d) nounwind {
> + %e = add i64 %d, 1
> + %retval = and i64 %e, 4294967295
> + ret i64 %retval
> +}
> +
> +define i32 @g(i8 %d) nounwind {
> + %e = add i8 %d, 1
> + %retval = zext i8 %e to i32
> + ret i32 %retval
> +}
> +define i32 @h(i16 %d) nounwind {
> + %e = add i16 %d, 1
> + %retval = zext i16 %e to i32
> + ret i32 %retval
> +}
> +define i64 @i(i8 %d) nounwind {
> + %e = add i8 %d, 1
> + %retval = zext i8 %e to i64
> + ret i64 %retval
> +}
> +define i64 @j(i16 %d) nounwind {
> + %e = add i16 %d, 1
> + %retval = zext i16 %e to i64
> + ret i64 %retval
> +}
> +define i64 @k(i32 %d) nounwind {
> + %e = add i32 %d, 1
> + %retval = zext i32 %e to i64
> + ret i64 %retval
> +}
>
> Added: llvm/trunk/test/CodeGen/X86/zext-inreg-1.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/zext-inreg-1.ll?rev=54147&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/zext-inreg-1.ll (added)
> +++ llvm/trunk/test/CodeGen/X86/zext-inreg-1.ll Mon Jul 28 17:18:25 2008
> @@ -0,0 +1,18 @@
> +; RUN: llvm-as < %s | llc -march=x86 | not grep and
> +
> +; These tests differ from the ones in zext-inreg-0.ll in that
> +; on x86-64 they do require and instructions.
> +
> +; These should use movzbl instead of 'and 255'.
> +; This related to not having ZERO_EXTEND_REG node.
> +
> +define i64 @g(i64 %d) nounwind {
> + %e = add i64 %d, 1
> + %retval = and i64 %e, 1099511627775
> + ret i64 %retval
> +}
> +define i64 @h(i64 %d) nounwind {
> + %e = add i64 %d, 1
> + %retval = and i64 %e, 281474976710655
> + ret i64 %retval
> +}
>
>
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