[llvm-commits] [llvm] r54039 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/vec_insert-7.ll

[Nate Begeman]

Author: sampo
Date: Fri Jul 25 14:05:58 2008
New Revision: 54039

URL: http://llvm.org/viewvc/llvm-project?rev=54039&view=rev
Log:
Disable mov{L, LP, HP, HLP, *DUP} shuffles for mmx
mmx needs its own fancy shuffle logic based on unpack; for now we get correct but awful code.

Also commit Mon Ping's VSETCC patch

Added:
    llvm/trunk/test/CodeGen/X86/vec_insert-7.ll
Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=54039&r1=54038&r2=54039&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jul 25 14:05:58 2008
@@ -3881,14 +3881,15 @@
       return V2;
     if (ISD::isBuildVectorAllZeros(V1.Val))
       return getVZextMovL(VT, VT, V2, DAG, Subtarget);
-    return Op;
+    if (!isMMX)
+      return Op;
   }
 
-  if (X86::isMOVSHDUPMask(PermMask.Val) ||
-      X86::isMOVSLDUPMask(PermMask.Val) ||
-      X86::isMOVHLPSMask(PermMask.Val) ||
-      X86::isMOVHPMask(PermMask.Val) ||
-      X86::isMOVLPMask(PermMask.Val))
+  if (!isMMX && (X86::isMOVSHDUPMask(PermMask.Val) ||
+                 X86::isMOVSLDUPMask(PermMask.Val) ||
+                 X86::isMOVHLPSMask(PermMask.Val) ||
+                 X86::isMOVHPMask(PermMask.Val) ||
+                 X86::isMOVLPMask(PermMask.Val)))
     return Op;
 
   if (ShouldXformToMOVHLPS(PermMask.Val) ||
@@ -4772,6 +4773,7 @@
 
     switch (SetCCOpcode) {
     default: break;
+    case ISD::SETOEQ:
     case ISD::SETEQ:  SSECC = 0; break;
     case ISD::SETOGT: 
     case ISD::SETGT: Swap = true; // Fallthrough
@@ -4782,7 +4784,7 @@
     case ISD::SETLE:
     case ISD::SETOLE: SSECC = 2; break;
     case ISD::SETUO:  SSECC = 3; break;
-    case ISD::SETONE:
+    case ISD::SETUNE:
     case ISD::SETNE:  SSECC = 4; break;
     case ISD::SETULE: Swap = true;
     case ISD::SETUGE: SSECC = 5; break;
@@ -4793,15 +4795,21 @@
     if (Swap)
       std::swap(Op0, Op1);
 
-    // In the one special case we can't handle, emit two comparisons.
+    // In the two special cases we can't handle, emit two comparisons.
     if (SSECC == 8) {
-      SDOperand UNORD, EQ;
-
-      assert(SetCCOpcode == ISD::SETUEQ && "Illegal FP comparison");
-      
-      UNORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
-      EQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
-      return DAG.getNode(ISD::OR, VT, UNORD, EQ);
+      if (SetCCOpcode == ISD::SETUEQ) {
+        SDOperand UNORD, EQ;
+        UNORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
+        EQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
+        return DAG.getNode(ISD::OR, VT, UNORD, EQ);
+      }
+      else if (SetCCOpcode == ISD::SETONE) {
+        SDOperand ORD, NEQ;
+        ORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
+        NEQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
+        return DAG.getNode(ISD::AND, VT, ORD, NEQ);
+      }
+      assert(0 && "Illegal FP comparison");
     }
     // Handle all other FP comparisons here.
     return DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));

Added: llvm/trunk/test/CodeGen/X86/vec_insert-7.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_insert-7.ll?rev=54039&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_insert-7.ll (added)
+++ llvm/trunk/test/CodeGen/X86/vec_insert-7.ll Fri Jul 25 14:05:58 2008
@@ -0,0 +1,8 @@
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep punpckldq
+
+define <2 x i32> @mmx_movzl(<2 x i32> %x) nounwind  {
+entry:
+	%tmp3 = insertelement <2 x i32> %x, i32 32, i32 0		; <<2 x i32>> [#uses=1]
+	%tmp8 = insertelement <2 x i32> %tmp3, i32 0, i32 1		; <<2 x i32>> [#uses=1]
+	ret <2 x i32> %tmp8
+}