[llvm-commits] [llvm] r53723 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp lib/CodeGen/SelectionDAG/LegalizeTypes.h test/CodeGen/PowerPC/2008-07-17-Fneg.ll

[Duncan Sands]

Author: baldrick
Date: Thu Jul 17 12:35:14 2008
New Revision: 53723

URL: http://llvm.org/viewvc/llvm-project?rev=53723&view=rev
Log:
LegalizeTypes support for what seems to be the
only missing ppc long double operations: FNEG
and FP_EXTEND.

Added:
    llvm/trunk/test/CodeGen/PowerPC/2008-07-17-Fneg.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=53723&r1=53722&r2=53723&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Thu Jul 17 12:35:14 2008
@@ -531,6 +531,8 @@
   case ISD::FADD:       ExpandFloatRes_FADD(N, Lo, Hi); break;
   case ISD::FDIV:       ExpandFloatRes_FDIV(N, Lo, Hi); break;
   case ISD::FMUL:       ExpandFloatRes_FMUL(N, Lo, Hi); break;
+  case ISD::FNEG:       ExpandFloatRes_FNEG(N, Lo, Hi); break;
+  case ISD::FP_EXTEND:  ExpandFloatRes_FP_EXTEND(N, Lo, Hi); break;
   case ISD::FSUB:       ExpandFloatRes_FSUB(N, Lo, Hi); break;
   case ISD::LOAD:       ExpandFloatRes_LOAD(N, Lo, Hi); break;
   case ISD::SINT_TO_FP:
@@ -609,6 +611,20 @@
   Lo = Call.getOperand(0); Hi = Call.getOperand(1);
 }
 
+void DAGTypeLegalizer::ExpandFloatRes_FNEG(SDNode *N, SDOperand &Lo,
+                                           SDOperand &Hi) {
+  GetExpandedFloat(N->getOperand(0), Lo, Hi);
+  Lo = DAG.getNode(ISD::FNEG, Lo.getValueType(), Lo);
+  Hi = DAG.getNode(ISD::FNEG, Hi.getValueType(), Hi);
+}
+
+void DAGTypeLegalizer::ExpandFloatRes_FP_EXTEND(SDNode *N, SDOperand &Lo,
+                                                SDOperand &Hi) {
+  MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+  Hi = DAG.getNode(ISD::FP_EXTEND, NVT, N->getOperand(0));
+  Lo = DAG.getConstantFP(APFloat(APInt(NVT.getSizeInBits(), 0)), NVT);
+}
+
 void DAGTypeLegalizer::ExpandFloatRes_FSUB(SDNode *N, SDOperand &Lo,
                                            SDOperand &Hi) {
   SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=53723&r1=53722&r2=53723&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Thu Jul 17 12:35:14 2008
@@ -374,6 +374,8 @@
   void ExpandFloatRes_FADD      (SDNode *N, SDOperand &Lo, SDOperand &Hi);
   void ExpandFloatRes_FDIV      (SDNode *N, SDOperand &Lo, SDOperand &Hi);
   void ExpandFloatRes_FMUL      (SDNode *N, SDOperand &Lo, SDOperand &Hi);
+  void ExpandFloatRes_FNEG      (SDNode *N, SDOperand &Lo, SDOperand &Hi);
+  void ExpandFloatRes_FP_EXTEND (SDNode *N, SDOperand &Lo, SDOperand &Hi);
   void ExpandFloatRes_FSUB      (SDNode *N, SDOperand &Lo, SDOperand &Hi);
   void ExpandFloatRes_LOAD      (SDNode *N, SDOperand &Lo, SDOperand &Hi);
   void ExpandFloatRes_XINT_TO_FP(SDNode *N, SDOperand &Lo, SDOperand &Hi);

Added: llvm/trunk/test/CodeGen/PowerPC/2008-07-17-Fneg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2008-07-17-Fneg.ll?rev=53723&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/2008-07-17-Fneg.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/2008-07-17-Fneg.ll Thu Jul 17 12:35:14 2008
@@ -0,0 +1,18 @@
+; RUN: llvm-as < %s | llc
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
+target triple = "powerpc-apple-darwin9"
+
+define hidden i64 @__fixunstfdi(ppc_fp128 %a) nounwind  {
+entry:
+	br i1 false, label %bb3, label %bb4
+
+bb3:		; preds = %entry
+	sub ppc_fp128 0xM80000000000000000000000000000000, 0xM00000000000000000000000000000000		; <ppc_fp128>:0 [#uses=1]
+	fptoui ppc_fp128 %0 to i32		; <i32>:1 [#uses=1]
+	zext i32 %1 to i64		; <i64>:2 [#uses=1]
+	sub i64 0, %2		; <i64>:3 [#uses=1]
+	ret i64 %3
+
+bb4:		; preds = %entry
+	ret i64 0
+}