[llvm-commits] [llvm] r53603 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp lib/CodeGen/SelectionDAG/LegalizeTypes.h test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll

[Duncan Sands]

Author: baldrick
Date: Tue Jul 15 05:14:24 2008
New Revision: 53603

URL: http://llvm.org/viewvc/llvm-project?rev=53603&view=rev
Log:
LegalizeTypes support for promotion of SIGN_EXTEND_INREG.

Added:
    llvm/trunk/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=53603&r1=53602&r2=53603&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Tue Jul 15 05:14:24 2008
@@ -66,6 +66,8 @@
   case ISD::SELECT_CC:   Result = PromoteIntRes_SELECT_CC(N); break;
   case ISD::SETCC:       Result = PromoteIntRes_SETCC(N); break;
   case ISD::SHL:         Result = PromoteIntRes_SHL(N); break;
+  case ISD::SIGN_EXTEND_INREG:
+                         Result = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
   case ISD::SRA:         Result = PromoteIntRes_SRA(N); break;
   case ISD::SRL:         Result = PromoteIntRes_SRL(N); break;
   case ISD::TRUNCATE:    Result = PromoteIntRes_TRUNCATE(N); break;
@@ -344,6 +346,12 @@
                      GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
 }
 
+SDOperand DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
+  SDOperand Op = GetPromotedInteger(N->getOperand(0));
+  return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op,
+                     N->getOperand(1));
+}
+
 SDOperand DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
   // The input may have strange things in the top bits of the registers, but
   // these operations don't care.  They may have weird bits going out, but

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=53603&r1=53602&r2=53603&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Tue Jul 15 05:14:24 2008
@@ -228,6 +228,7 @@
   SDOperand PromoteIntRes_SETCC(SDNode *N);
   SDOperand PromoteIntRes_SHL(SDNode *N);
   SDOperand PromoteIntRes_SimpleIntBinOp(SDNode *N);
+  SDOperand PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N);
   SDOperand PromoteIntRes_SRA(SDNode *N);
   SDOperand PromoteIntRes_SRL(SDNode *N);
   SDOperand PromoteIntRes_TRUNCATE(SDNode *N);

Added: llvm/trunk/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll?rev=53603&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll Tue Jul 15 05:14:24 2008
@@ -0,0 +1,17 @@
+; RUN: llvm-as < %s | llc
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
+target triple = "powerpc-apple-darwin9"
+
+define i16 @t(i16* %dct) signext nounwind  {
+entry:
+         load i16* null, align 2         ; <i16>:0 [#uses=2]
+         lshr i16 %0, 11         ; <i16>:1 [#uses=0]
+         trunc i16 %0 to i8              ; <i8>:2 [#uses=1]
+         sext i8 %2 to i16               ; <i16>:3 [#uses=1]
+         add i16 0, %3           ; <i16>:4 [#uses=1]
+         sext i16 %4 to i32              ; <i32>:5 [#uses=1]
+         %dcval.0.in = shl i32 %5, 0             ; <i32> [#uses=1]
+         %dcval.0 = trunc i32 %dcval.0.in to i16         ; <i16>  [#uses=1]
+         store i16 %dcval.0, i16* %dct, align 2
+         ret i16 0
+}