[llvm-commits] [llvm] r53502 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGISel.h include/llvm/Support/Timer.h lib/CodeGen/SelectionDAG/ScheduleDAG.cpp lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp lib/Support/Timer.cpp
Evan Cheng
evan.cheng at apple.com
Fri Jul 11 18:38:51 PDT 2008
Author: evancheng
Date: Fri Jul 11 20:38:51 2008
New Revision: 53502
URL: http://llvm.org/viewvc/llvm-project?rev=53502&view=rev
Log:
Back out 53476 and 53480 for now. Somehow they cause llc to miscompile 179.art.
Modified:
llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
llvm/trunk/include/llvm/Support/Timer.h
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
llvm/trunk/lib/Support/Timer.cpp
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=53502&r1=53501&r2=53502&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Fri Jul 11 20:38:51 2008
@@ -30,7 +30,6 @@
class FunctionLoweringInfo;
class HazardRecognizer;
class CollectorMetadata;
- class ScheduleDAG;
/// SelectionDAGISel - This is the common base class used for SelectionDAG-based
/// pattern-matching instruction selectors.
@@ -192,9 +191,9 @@
void ComputeLiveOutVRegInfo(SelectionDAG &DAG);
- /// Pick a safe ordering for instructions for each target node in the
+ /// Pick a safe ordering and emit instructions for each target node in the
/// graph.
- ScheduleDAG *Schedule(SelectionDAG &DAG);
+ void ScheduleAndEmitDAG(SelectionDAG &DAG);
/// SwitchCases - Vector of CaseBlock structures used to communicate
/// SwitchInst code generation information.
Modified: llvm/trunk/include/llvm/Support/Timer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Timer.h?rev=53502&r1=53501&r2=53502&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/Timer.h (original)
+++ llvm/trunk/include/llvm/Support/Timer.h Fri Jul 11 20:38:51 2008
@@ -132,8 +132,6 @@
///
struct NamedRegionTimer : public TimeRegion {
explicit NamedRegionTimer(const std::string &Name);
- explicit NamedRegionTimer(const std::string &Name,
- const std::string &GroupName);
};
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp?rev=53502&r1=53501&r2=53502&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Fri Jul 11 20:38:51 2008
@@ -1135,11 +1135,6 @@
///
MachineBasicBlock *ScheduleDAG::Run() {
Schedule();
-
- DOUT << "*** Final schedule ***\n";
- DEBUG(dumpSchedule());
- DOUT << "\n";
-
return BB;
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp?rev=53502&r1=53501&r2=53502&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Fri Jul 11 20:38:51 2008
@@ -99,6 +99,13 @@
ListScheduleTopDown();
AvailableQueue->releaseState();
+
+ DOUT << "*** Final schedule ***\n";
+ DEBUG(dumpSchedule());
+ DOUT << "\n";
+
+ // Emit in scheduled order
+ EmitSchedule();
}
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=53502&r1=53501&r2=53502&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Fri Jul 11 20:38:51 2008
@@ -204,6 +204,13 @@
if (!Fast)
CommuteNodesToReducePressure();
+
+ DOUT << "*** Final schedule ***\n";
+ DEBUG(dumpSchedule());
+ DOUT << "\n";
+
+ // Emit in scheduled order
+ EmitSchedule();
}
/// CommuteNodesToReducePressure - If a node is two-address and commutable, and
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=53502&r1=53501&r2=53502&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Jul 11 20:38:51 2008
@@ -5284,11 +5284,10 @@
void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
DOUT << "Lowered selection DAG:\n";
DEBUG(DAG.dump());
- std::string GroupName = "Instruction Selection and Scheduling";
// Run the DAG combiner in pre-legalize mode.
if (TimePassesIsEnabled) {
- NamedRegionTimer T("DAG Combining 1", GroupName);
+ NamedRegionTimer T("DAG Combining 1");
DAG.Combine(false, *AA);
} else {
DAG.Combine(false, *AA);
@@ -5305,7 +5304,7 @@
}
if (TimePassesIsEnabled) {
- NamedRegionTimer T("DAG Legalization", GroupName);
+ NamedRegionTimer T("DAG Legalization");
DAG.Legalize();
} else {
DAG.Legalize();
@@ -5316,7 +5315,7 @@
// Run the DAG combiner in post-legalize mode.
if (TimePassesIsEnabled) {
- NamedRegionTimer T("DAG Combining 2", GroupName);
+ NamedRegionTimer T("DAG Combining 2");
DAG.Combine(true, *AA);
} else {
DAG.Combine(true, *AA);
@@ -5333,41 +5332,24 @@
// Third, instruction select all of the operations to machine code, adding the
// code to the MachineBasicBlock.
if (TimePassesIsEnabled) {
- NamedRegionTimer T("Instruction Selection", GroupName);
+ NamedRegionTimer T("Instruction Selection");
InstructionSelect(DAG);
} else {
InstructionSelect(DAG);
}
- // Schedule machine code.
- ScheduleDAG *Scheduler;
- if (TimePassesIsEnabled) {
- NamedRegionTimer T("Instruction Scheduling", GroupName);
- Scheduler = Schedule(DAG);
- } else {
- Scheduler = Schedule(DAG);
- }
-
// Emit machine code to BB. This can change 'BB' to the last block being
// inserted into.
if (TimePassesIsEnabled) {
- NamedRegionTimer T("Instruction Creation", GroupName);
- Scheduler->EmitSchedule();
- } else {
- Scheduler->EmitSchedule();
- }
-
- // Free the scheduler state.
- if (TimePassesIsEnabled) {
- NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
- delete Scheduler;
+ NamedRegionTimer T("Instruction Scheduling");
+ ScheduleAndEmitDAG(DAG);
} else {
- delete Scheduler;
+ ScheduleAndEmitDAG(DAG);
}
// Perform target specific isel post processing.
if (TimePassesIsEnabled) {
- NamedRegionTimer T("Instruction Selection Post Processing", GroupName);
+ NamedRegionTimer T("Instruction Selection Post Processing");
InstructionSelectPostProcessing(DAG);
} else {
InstructionSelectPostProcessing(DAG);
@@ -5615,10 +5597,10 @@
}
-/// Schedule - Pick a safe ordering for instructions for each
+//===----------------------------------------------------------------------===//
+/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
/// target node in the graph.
-///
-ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) {
+void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
if (ViewSchedDAGs) DAG.viewGraph();
RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
@@ -5628,11 +5610,12 @@
RegisterScheduler::setDefault(Ctor);
}
- ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, FastISel);
- BB = Scheduler->Run();
+ ScheduleDAG *SL = Ctor(this, &DAG, BB, FastISel);
+ BB = SL->Run();
+
+ if (ViewSUnitDAGs) SL->viewGraph();
- if (ViewSUnitDAGs) Scheduler->viewGraph();
- return Scheduler;
+ delete SL;
}
Modified: llvm/trunk/lib/Support/Timer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Timer.cpp?rev=53502&r1=53501&r2=53502&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Timer.cpp (original)
+++ llvm/trunk/lib/Support/Timer.cpp Fri Jul 11 20:38:51 2008
@@ -182,51 +182,19 @@
// NamedRegionTimer Implementation
//===----------------------------------------------------------------------===//
-namespace {
-
-typedef std::map<std::string, Timer> Name2Timer;
-typedef std::map<std::string, std::pair<TimerGroup, Name2Timer> > Name2Pair;
-
-}
-
-static ManagedStatic<Name2Timer> NamedTimers;
-
-static ManagedStatic<Name2Pair> NamedGroupedTimers;
+static ManagedStatic<std::map<std::string, Timer> > NamedTimers;
static Timer &getNamedRegionTimer(const std::string &Name) {
- Name2Timer::iterator I = NamedTimers->find(Name);
+ std::map<std::string, Timer>::iterator I = NamedTimers->find(Name);
if (I != NamedTimers->end())
return I->second;
return NamedTimers->insert(I, std::make_pair(Name, Timer(Name)))->second;
}
-static Timer &getNamedRegionTimer(const std::string &Name,
- const std::string &GroupName) {
-
- Name2Pair::iterator I = NamedGroupedTimers->find(GroupName);
- if (I == NamedGroupedTimers->end()) {
- TimerGroup TG(GroupName);
- std::pair<TimerGroup, Name2Timer> Pair(TG, Name2Timer());
- I = NamedGroupedTimers->insert(I, std::make_pair(GroupName, Pair));
- }
-
- Name2Timer::iterator J = I->second.second.find(Name);
- if (J == I->second.second.end())
- J = I->second.second.insert(J,
- std::make_pair(Name,
- Timer(Name,
- I->second.first)));
-
- return J->second;
-}
-
NamedRegionTimer::NamedRegionTimer(const std::string &Name)
: TimeRegion(getNamedRegionTimer(Name)) {}
-NamedRegionTimer::NamedRegionTimer(const std::string &Name,
- const std::string &GroupName)
- : TimeRegion(getNamedRegionTimer(Name, GroupName)) {}
//===----------------------------------------------------------------------===//
// TimerGroup Implementation
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