[llvm-commits] [llvm] r53410 - in /llvm/trunk: lib/Target/PowerPC/PPCISelLowering.cpp test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll

[Chris Lattner]

Author: lattner
Date: Thu Jul 10 11:33:38 2008
New Revision: 53410

URL: http://llvm.org/viewvc/llvm-project?rev=53410&view=rev
Log:
Fix an altivec constant miscompilation that Duncan found through
his work on legalizetypes.

Added:
    llvm/trunk/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll
Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=53410&r1=53409&r2=53410&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Jul 10 11:33:38 2008
@@ -3399,8 +3399,10 @@
     // If this value is in the range [-32,30] and is even, use:
     //    tmp = VSPLTI[bhw], result = add tmp, tmp
     if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
-      Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
-      return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
+      SDOperand Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG);
+      Res = DAG.getNode(ISD::ADD, Res.getValueType(), Res, Res);
+      return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
+
     }
     
     // If this is 0x8000_0000 x 4, turn into vspltisw + vslw.  If it is 

Added: llvm/trunk/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll?rev=53410&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll Thu Jul 10 11:33:38 2008
@@ -0,0 +1,10 @@
+; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vadduhm
+; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsubuhm
+
+define <4 x i32> @test() nounwind {
+	ret <4 x i32> < i32 4293066722, i32 4293066722, i32 4293066722, i32 4293066722>
+}
+
+define <4 x i32> @test2() nounwind {
+	ret <4 x i32> < i32 1114129, i32 1114129, i32 1114129, i32 1114129>
+}