[llvm-commits] [llvm] r53030 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

[Chris Lattner]

Author: lattner
Date: Wed Jul  2 12:01:57 2008
New Revision: 53030

URL: http://llvm.org/viewvc/llvm-project?rev=53030&view=rev
Log:
instead of aborting on shifts of i1, just implicitly fold them.
The dag combiner can produce a shift of i1 when folding icmp i1's.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=53030&r1=53029&r2=53030&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Jul  2 12:01:57 2008
@@ -2192,7 +2192,13 @@
     assert(VT == N1.getValueType() &&
            "Shift operators return type must be the same as their first arg");
     assert(VT.isInteger() && N2.getValueType().isInteger() &&
-           VT != MVT::i1 && "Shifts only work on integers");
+           "Shifts only work on integers");
+
+    // Always fold shifts of i1 values so the code generator doesn't need to
+    // handle them.  Since we know the size of the shift has to be less than the
+    // size of the value, the shift/rotate count is guaranteed to be zero.
+    if (VT == MVT::i1)
+      return N1;
     break;
   case ISD::FP_ROUND_INREG: {
     MVT EVT = cast<VTSDNode>(N2)->getVT();