[llvm-commits] [llvm] r52918 - /llvm/trunk/include/llvm/Target/TargetLowering.h

[Dan Gohman]

Author: djg
Date: Mon Jun 30 15:33:57 2008
New Revision: 52918

URL: http://llvm.org/viewvc/llvm-project?rev=52918&view=rev
Log:
Change bools to 1-bit bitfields to shrink ArgListEntry slightly.

Modified:
    llvm/trunk/include/llvm/Target/TargetLowering.h

Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=52918&r1=52917&r2=52918&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Mon Jun 30 15:33:57 2008
@@ -975,12 +975,12 @@
   struct ArgListEntry {
     SDOperand Node;
     const Type* Ty;
-    bool isSExt;
-    bool isZExt;
-    bool isInReg;
-    bool isSRet;
-    bool isNest;
-    bool isByVal;
+    bool isSExt  : 1;
+    bool isZExt  : 1;
+    bool isInReg : 1;
+    bool isSRet  : 1;
+    bool isNest  : 1;
+    bool isByVal : 1;
     uint16_t Alignment;
 
     ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),