[llvm-commits] [llvm-gcc-4.2] r51725 - /llvm-gcc-4.2/trunk/gcc/config/spu/spu.c

[Scott Michel]

Author: pingbak
Date: Thu May 29 22:07:41 2008
New Revision: 51725

URL: http://llvm.org/viewvc/llvm-project?rev=51725&view=rev
Log:
Clean up the instruction scheduling preprocessor disabling blocks to be consistent.

Modified:
    llvm-gcc-4.2/trunk/gcc/config/spu/spu.c

Modified: llvm-gcc-4.2/trunk/gcc/config/spu/spu.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/spu/spu.c?rev=51725&r1=51724&r2=51725&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/spu/spu.c (original)
+++ llvm-gcc-4.2/trunk/gcc/config/spu/spu.c Thu May 29 22:07:41 2008
@@ -99,7 +99,7 @@
 static rtx frame_emit_add_imm (rtx dst, rtx src, HOST_WIDE_INT imm,
 			       rtx scratch);
 /* LLVM LOCAL begin */
-#ifndef ENABLE_LLVM
+#ifndef INSN_SCHEDULING
 static void emit_nop_for_insn (rtx insn);
 static bool insn_clobbers_hbr (rtx insn);
 static void spu_emit_branch_hint (rtx before, rtx branch, rtx target,
@@ -141,7 +141,7 @@
 static void fix_range (const char *);
 static void spu_encode_section_info (tree, rtx, int);
 /* LLVM LOCAL begin */
-#ifndef ENABLE_LLVM
+#ifndef INSN_SCHEDULING
 static tree spu_builtin_mul_widen_even (tree);
 static tree spu_builtin_mul_widen_odd (tree);
 #endif
@@ -1819,7 +1819,7 @@
 };
 
 /* LLVM LOCAL begin */
-#ifndef ENABLE_LLVM
+#ifndef INSN_SCHEDULING
 /* The special $hbr register is used to prevent the insn scheduler from
    moving hbr insns across instructions which invalidate them.  It
    should only be used in a clobber, and this function searches for
@@ -1956,7 +1956,7 @@
 insert_branch_hints (void)
 {
 /* LLVM LOCAL begin */
-#ifndef ENABLE_LLVM
+#ifndef INSN_SCHEDULING
   struct spu_bb_info *spu_bb_info;
   rtx branch, insn, next;
   rtx branch_target = 0;
@@ -2132,7 +2132,7 @@
 }
 
 /* LLVM LOCAL begin */
-#ifndef ENABLE_LLVM
+#ifndef INSN_SCHEDULING
 /* Emit a nop for INSN such that the two will dual issue.  This assumes
    INSN is 8-byte aligned.  When INSN is inline asm we emit an lnop.
    We check for TImode to handle a MULTI1 insn which has dual issued its
@@ -2162,7 +2162,7 @@
 insert_nops (void)
 {
 /* LLVM LOCAL begin */
-#ifndef ENABLE_LLVM
+#ifndef INSN_SCHEDULING
   rtx insn, next_insn, prev_insn;
   int length;
   int addr;
@@ -5041,7 +5041,7 @@
 }
 
 /* LLVM LOCAL begin */
-#ifndef ENABLE_LLVM
+#ifndef INSN_SCHEDULING
 /* Implement targetm.vectorize.builtin_mul_widen_even.  */
 static tree
 spu_builtin_mul_widen_even (tree type)
@@ -5075,7 +5075,7 @@
       return NULL_TREE;
     }
 }
-#endif /* ENABLE_LLVM */
+#endif /* INSN_SCHEDULING */
 /* LLVM LOCAL end */
 
 /* Implement targetm.vectorize.builtin_mask_for_load.  */