[llvm-commits] [llvm] r51660 - in /llvm/trunk: include/llvm/Target/TargetInstrDesc.h lib/CodeGen/MachineInstr.cpp lib/Target/Target.td utils/TableGen/CodeGenInstruction.cpp utils/TableGen/CodeGenInstruction.h utils/TableGen/InstrInfoEmitter.cpp
Evan Cheng
evan.cheng at apple.com
Wed May 28 16:50:21 PDT 2008
Please don't add another flag. For now, please check if an instruction
is rematerializable && !mayload.
Evan
On May 28, 2008, at 3:54 PM, Bill Wendling wrote:
> Author: void
> Date: Wed May 28 17:54:52 2008
> New Revision: 51660
>
> URL: http://llvm.org/viewvc/llvm-project?rev=51660&view=rev
> Log:
> Add a flag to indicate that an instruction is as cheap (or cheaper)
> than a move
> instruction to execute. This can be used for transformations (like
> two-address
> conversion) to remat an instruction instead of generating a "move"
> instruction. The idea is to decrease the live ranges and register
> pressure and
> all that jazz.
>
> Modified:
> llvm/trunk/include/llvm/Target/TargetInstrDesc.h
> llvm/trunk/lib/CodeGen/MachineInstr.cpp
> llvm/trunk/lib/Target/Target.td
> llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
> llvm/trunk/utils/TableGen/CodeGenInstruction.h
> llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
>
> Modified: llvm/trunk/include/llvm/Target/TargetInstrDesc.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrDesc.h?rev=51660&r1=51659&r2=51660&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/include/llvm/Target/TargetInstrDesc.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetInstrDesc.h Wed May 28
> 17:54:52 2008
> @@ -95,7 +95,8 @@
> Commutable,
> ConvertibleTo3Addr,
> UsesCustomDAGSchedInserter,
> - Rematerializable
> + Rematerializable,
> + CheapAsAMove
> };
> }
>
> @@ -387,6 +388,15 @@
> bool isRematerializable() const {
> return Flags & (1 << TID::Rematerializable);
> }
> +
> + /// isAsCheapAsAMove - Returns true if this instruction has the
> same cost (or
> + /// less) than a move instruction. This is useful during certain
> types of
> + /// rematerializations (e.g., during two-address conversion)
> where we would
> + /// like to remat the instruction, but not if it costs more than
> moving the
> + /// instruction into the appropriate register.
> + bool isAsCheapAsAMove() const {
> + return Flags & (1 << TID::CheapAsAMove);
> + }
> };
>
> } // end namespace llvm
>
> Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=51660&r1=51659&r2=51660&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Wed May 28 17:54:52 2008
> @@ -639,9 +639,9 @@
> }
> }
>
> -/// isSafeToMove - Return true if it is safe to this instruction.
> If SawStore
> -/// true, it means there is a store (or call) between the
> instruction the
> -/// localtion and its intended destination.
> +/// isSafeToMove - Return true if it is safe to this instruction.
> If SawStore is
> +/// set to true, it means that there is a store (or call) between the
> +/// instruction's location and its intended destination.
> bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, bool
> &SawStore) {
> // Ignore stuff that we obviously can't move.
> if (TID->mayStore() || TID->isCall()) {
>
> Modified: llvm/trunk/lib/Target/Target.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Target.td?rev=51660&r1=51659&r2=51660&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/Target.td (original)
> +++ llvm/trunk/lib/Target/Target.td Wed May 28 17:54:52 2008
> @@ -203,22 +203,25 @@
> bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing
> special help.
> bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow
> chains?
> bit isNotDuplicable = 0; // Is it unsafe to duplicate this
> instruction?
> + bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move
> instruction.
>
> // Side effect flags - When set, the flags have these meanings:
> //
> // hasSideEffects - The instruction has side effects that are not
> // captured by any operands of the instruction or other flags.
> + //
> // mayHaveSideEffects - Some instances of the instruction can
> have side
> // effects. The virtual method "isReallySideEffectFree" is
> called to
> // determine this. Load instructions are an example of where
> this is
> // useful. In general, loads always have side effects. However,
> loads from
> // constant pools don't. Individual back ends make this
> determination.
> + //
> // neverHasSideEffects - Set on an instruction with no pattern if
> it has no
> // side effects.
> bit hasSideEffects = 0;
> bit mayHaveSideEffects = 0;
> bit neverHasSideEffects = 0;
> -
> +
> InstrItinClass Itinerary = NoItinerary;// Execution steps used for
> scheduling.
>
> string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
>
> Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=51660&r1=51659&r2=51660&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original)
> +++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Wed May 28
> 17:54:52 2008
> @@ -99,6 +99,7 @@
> hasSideEffects = R->getValueAsBit("hasSideEffects");
> mayHaveSideEffects = R->getValueAsBit("mayHaveSideEffects");
> neverHasSideEffects = R->getValueAsBit("neverHasSideEffects");
> + isAsCheapAsAMove = R->getValueAsBit("isAsCheapAsAMove");
> hasOptionalDef = false;
> isVariadic = false;
>
>
> Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.h?rev=51660&r1=51659&r2=51660&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/utils/TableGen/CodeGenInstruction.h (original)
> +++ llvm/trunk/utils/TableGen/CodeGenInstruction.h Wed May 28
> 17:54:52 2008
> @@ -102,7 +102,10 @@
> bool hasCtrlDep;
> bool isNotDuplicable;
> bool hasOptionalDef;
> - bool hasSideEffects, mayHaveSideEffects, neverHasSideEffects;
> + bool hasSideEffects;
> + bool mayHaveSideEffects;
> + bool neverHasSideEffects;
> + bool isAsCheapAsAMove;
>
> /// ParseOperandName - Parse an operand name like "$foo" or
> "$foo.bar",
> /// where $foo is a whole operand and $foo.bar refers to a
> suboperand.
>
> Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=51660&r1=51659&r2=51660&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Wed May 28
> 17:54:52 2008
> @@ -208,26 +208,27 @@
> << ",\t\"" << Inst.TheDef->getName() << "\", 0";
>
> // Emit all of the target indepedent flags...
> - if (Inst.isReturn) OS << "|(1<<TID::Return)";
> - if (Inst.isBranch) OS << "|(1<<TID::Branch)";
> - if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)";
> - if (Inst.isBarrier) OS << "|(1<<TID::Barrier)";
> - if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
> - if (Inst.isCall) OS << "|(1<<TID::Call)";
> - if (Inst.isSimpleLoad) OS << "|(1<<TID::SimpleLoad)";
> - if (Inst.mayLoad) OS << "|(1<<TID::MayLoad)";
> - if (Inst.mayStore) OS << "|(1<<TID::MayStore)";
> - if (Inst.isPredicable) OS << "|(1<<TID::Predicable)";
> + if (Inst.isReturn) OS << "|(1<<TID::Return)";
> + if (Inst.isBranch) OS << "|(1<<TID::Branch)";
> + if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)";
> + if (Inst.isBarrier) OS << "|(1<<TID::Barrier)";
> + if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
> + if (Inst.isCall) OS << "|(1<<TID::Call)";
> + if (Inst.isSimpleLoad) OS << "|(1<<TID::SimpleLoad)";
> + if (Inst.mayLoad) OS << "|(1<<TID::MayLoad)";
> + if (Inst.mayStore) OS << "|(1<<TID::MayStore)";
> + if (Inst.isPredicable) OS << "|(1<<TID::Predicable)";
> if (Inst.isConvertibleToThreeAddress) OS << "|
> (1<<TID::ConvertibleTo3Addr)";
> - if (Inst.isCommutable) OS << "|(1<<TID::Commutable)";
> - if (Inst.isTerminator) OS << "|(1<<TID::Terminator)";
> + if (Inst.isCommutable) OS << "|(1<<TID::Commutable)";
> + if (Inst.isTerminator) OS << "|(1<<TID::Terminator)";
> if (Inst.isReMaterializable) OS << "|(1<<TID::Rematerializable)";
> if (Inst.isNotDuplicable) OS << "|(1<<TID::NotDuplicable)";
> if (Inst.hasOptionalDef) OS << "|(1<<TID::HasOptionalDef)";
> if (Inst.usesCustomDAGSchedInserter)
> OS << "|(1<<TID::UsesCustomDAGSchedInserter)";
> if (Inst.isVariadic) OS << "|(1<<TID::Variadic)";
> - if (Inst.hasSideEffects) OS << "|
> (1<<TID::UnmodeledSideEffects)";
> + if (Inst.hasSideEffects) OS << "|
> (1<<TID::UnmodeledSideEffects)";
> + if (Inst.isAsCheapAsAMove) OS << "|(1<<TID::CheapAsAMove)";
> OS << ", 0";
>
> // Emit all of the target-specific flags...
>
>
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