[llvm-commits] [llvm] r51115 - in /llvm/trunk/lib/CodeGen/SelectionDAG: ScheduleDAG.cpp ScheduleDAGRRList.cpp SelectionDAGISel.cpp

[Chris Lattner]

On May 14, 2008, at 1:07 PM, Evan Cheng wrote:
> URL: http://llvm.org/viewvc/llvm-project?rev=51115&view=rev
> Log:
> Silence some compiler warnings.

This introduces new compiler warnings "isNew computation has no side  
effects".  How about "isNew = isNew;" ?  We use this idiom in other  
places,

-Chris

>
>
> Modified:
>    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp?rev=51115&r1=51114&r2=51115&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Wed May 14  
> 15:07:51 2008
> @@ -407,6 +407,7 @@
>     if (InstanceNo > 0)
>       VRBaseMap.erase(SDOperand(Node, ResNo));
>     bool isNew =  
> VRBaseMap.insert(std::make_pair(SDOperand(Node,ResNo),SrcReg));
> +    isNew; // Silence compiler warning.
>     assert(isNew && "Node emitted out of order - early");
>     return;
>   }
> @@ -465,6 +466,7 @@
>   if (InstanceNo > 0)
>     VRBaseMap.erase(SDOperand(Node, ResNo));
>   bool isNew =  
> VRBaseMap.insert(std::make_pair(SDOperand(Node,ResNo), VRBase));
> +  isNew; // Silence compiler warning.
>   assert(isNew && "Node emitted out of order - early");
> }
>
> @@ -522,6 +524,7 @@
>     }
>
>     bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,i),  
> VRBase));
> +    isNew; // Silence compiler warning.
>     assert(isNew && "Node emitted out of order - early");
>   }
> }
> @@ -719,9 +722,11 @@
>
>     if (VRBase) {
>       // Grab the destination register
> +#ifndef NDEBUG
>       const TargetRegisterClass *DRC = MRI.getRegClass(VRBase);
>       assert(SRC && DRC && SRC == DRC &&
>              "Source subregister and destination must have the same  
> class");
> +#endif
>     } else {
>       // Create the reg
>       assert(SRC && "Couldn't find source register class");
> @@ -772,6 +777,7 @@
>     assert(0 && "Node is not insert_subreg, extract_subreg, or  
> subreg_to_reg");
>
>   bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,0),  
> VRBase));
> +  isNew; // Silence compiler warning.
>   assert(isNew && "Node emitted out of order - early");
> }
>
> @@ -799,10 +805,10 @@
>     unsigned NumResults = CountResults(Node);
>     unsigned NodeOperands = CountOperands(Node);
>     unsigned MemOperandsEnd = ComputeMemOperandsEnd(Node);
> -    unsigned NumMIOperands = NodeOperands + NumResults;
>     bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
>                           II.getImplicitDefs() != 0;
> #ifndef NDEBUG
> +    unsigned NumMIOperands = NodeOperands + NumResults;
>     assert((II.getNumOperands() == NumMIOperands ||
>             HasPhysRegOuts || II.isVariadic()) &&
>            "#operands for dag node doesn't match .td file!");
> @@ -999,6 +1005,7 @@
>       assert(I->Reg && "Unknown physical register!");
>       unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
>       bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase));
> +      isNew; // Silence compiler warning.
>       assert(isNew && "Node emitted out of order - early");
>       TII->copyRegToReg(*BB, BB->end(), VRBase, I->Reg,
>                         SU->CopyDstRC, SU->CopySrcRC);
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=51115&r1=51114&r2=51115&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp  
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Wed  
> May 14 15:07:51 2008
> @@ -1317,6 +1317,7 @@
>     void remove(SUnit *SU) {
>       assert(!Queue.empty() && "Queue is empty!");
>       size_t RemovedNum = Queue.erase(SU);
> +      RemovedNum; // Silence compiler warning.
>       assert(RemovedNum > 0 && "Not in queue!");
>       assert(RemovedNum == 1 && "Multiple times in the queue!");
>       SU->NodeQueueId = 0;
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=51115&r1=51114&r2=51115&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp  
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed May  
> 14 15:07:51 2008
> @@ -807,7 +807,7 @@
>       unsigned NumRegs =
>         TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT,  
> NumIntermediates,
>                                    RegisterVT);
> -
> +      NumRegs; // Silence a compiler warning.
>       assert(NumRegs == NumParts && "Part count doesn't match vector  
> breakdown!");
>       assert(RegisterVT == PartVT && "Part type doesn't match vector  
> breakdown!");
>       assert(RegisterVT == Parts[0].getValueType() &&
> @@ -1024,6 +1024,7 @@
>     DAG.getTargetLoweringInfo()
>       .getVectorTypeBreakdown(ValueVT, IntermediateVT,  
> NumIntermediates,
>                               RegisterVT);
> +  NumRegs; // Silence a compiler warning.
>   unsigned NumElements = MVT::getVectorNumElements(ValueVT);
>
>   assert(NumRegs == NumParts && "Part count doesn't match vector  
> breakdown!");
> @@ -3752,14 +3753,13 @@
>     // If this is an expanded reference, add the rest of the regs to  
> Regs.
>     if (NumRegs != 1) {
>       TargetRegisterClass::iterator I = PhysReg.second->begin();
> -      TargetRegisterClass::iterator E = PhysReg.second->end();
>       for (; *I != PhysReg.first; ++I)
> -        assert(I != E && "Didn't find reg!");
> +        assert(I != PhysReg.second->end() && "Didn't find reg!");
>
>       // Already added the first reg.
>       --NumRegs; ++I;
>       for (; NumRegs; --NumRegs, ++I) {
> -        assert(I != E && "Ran out of registers to allocate!");
> +        assert(I != PhysReg.second->end() && "Ran out of registers  
> to allocate!");
>         Regs.push_back(*I);
>       }
>     }
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits