[llvm-commits] [llvm] r51000 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86ISelLowering.h X86InstrSSE.td

[Evan Cheng]

On May 12, 2008, at 1:34 PM, Nate Begeman wrote:
>
>
>   if (Subtarget->hasMMX()) {
> @@ -614,6 +615,7 @@
>     setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v4f32, Custom);
>     setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
>     setOperationAction(ISD::SELECT,             MVT::v4f32, Custom);
> +    setOperationAction(ISD::VSETCC,             MVT::v4f32, Legal);
>   }
>
>   if (Subtarget->hasSSE2()) {
> @@ -639,6 +641,12 @@
>     setOperationAction(ISD::FSQRT,              MVT::v2f64, Legal);
>     setOperationAction(ISD::FNEG,               MVT::v2f64, Custom);
>
> +    setOperationAction(ISD::VSETCC,             MVT::v2f64, Legal);
> +    setOperationAction(ISD::VSETCC,             MVT::v16i8, Legal);
> +    setOperationAction(ISD::VSETCC,             MVT::v8i16, Legal);
> +    setOperationAction(ISD::VSETCC,             MVT::v4i32, Legal);
> +    setOperationAction(ISD::VSETCC,             MVT::v2i64, Legal);
> +

Is VSETCC legal for v4f32 and v2f64? I don't see how they are isel'd.

Thanks,

Evan

>
>     setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v16i8, Custom);
>     setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v8i16, Custom);
>     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v8i16, Custom);
> @@ -686,6 +694,7 @@
>     setOperationAction(ISD::LOAD,               MVT::v2i64, Legal);
>     setOperationAction(ISD::SELECT,             MVT::v2f64, Custom);
>     setOperationAction(ISD::SELECT,             MVT::v2i64, Custom);
> +
>   }
>
>   if (Subtarget->hasSSE41()) {
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=51000&r1=50999&r2=51000&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Mon May 12 15:34:32  
> 2008
> @@ -565,7 +565,6 @@
>     MachineBasicBlock  
> *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
>                                                            
> MachineBasicBlock *BB,
>                                                           unsigned  
> cmovOpc);
> -
>   };
> }
>
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=51000&r1=50999&r2=51000&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon May 12 15:34:32 2008
> @@ -161,6 +161,22 @@
>   return getI32Imm(N->getValue() >> 3);
> }]>;
>
> +def SSE_CC_imm  : SDNodeXForm<cond, [{
> +  unsigned Val;
> +  switch (N->get()) {
> +  default: Val = 0; assert(0 && "Unexpected CondCode"); break;
> +  case ISD::SETOEQ: Val = 0; break;
> +  case ISD::SETOLT: Val = 1; break;
> +  case ISD::SETOLE: Val = 2; break;
> +  case ISD::SETUO:  Val = 3; break;
> +  case ISD::SETONE: Val = 4; break;
> +  case ISD::SETOGE: Val = 5; break;
> +  case ISD::SETOGT: Val = 6; break;
> +  case ISD::SETO:   Val = 7; break;
> +  }
> +  return getI8Imm(Val);
> +}]>;
> +
> // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask  
> to PSHUF*,
> // SHUFP* etc. imm.
> def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
> @@ -255,6 +271,7 @@
>   return X86::isSHUFPMask(N);
> }], SHUFFLE_get_shuf_imm>;
>
> +
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
> // SSE scalar FP Instructions
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
> @@ -855,16 +872,20 @@
>
> let Constraints = "$src1 = $dst" in {
>   def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
> -                      (outs VR128:$dst), (ins VR128:$src1,  
> VR128:$src, SSECC:$cc),
> -                      "cmp${cc}ps\t{$src, $dst|$dst, $src}",
> -                      [(set VR128:$dst, (int_x86_sse_cmp_ps  
> VR128:$src1,
> -                                         VR128:$src, imm:$cc))]>;
> +                    (outs VR128:$dst), (ins VR128:$src1,  
> VR128:$src, SSECC:$cc),
> +                    "cmp${cc}ps\t{$src, $dst|$dst, $src}",
> +                    [(set VR128:$dst, (int_x86_sse_cmp_ps  
> VR128:$src1,
> +                                                        VR128:$src,  
> imm:$cc))]>;
>   def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
> -                      (outs VR128:$dst), (ins VR128:$src1, f128mem: 
> $src, SSECC:$cc),
> -                      "cmp${cc}ps\t{$src, $dst|$dst, $src}",
> -                      [(set VR128:$dst, (int_x86_sse_cmp_ps  
> VR128:$src1,
> -                                         (load addr:$src), imm: 
> $cc))]>;
> -}
> +                  (outs VR128:$dst), (ins VR128:$src1, f128mem: 
> $src, SSECC:$cc),
> +                  "cmp${cc}ps\t{$src, $dst|$dst, $src}",
> +                  [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
> +                                                  (load addr:$src),  
> imm:$cc))]>;
> +}
> +def : Pat<(v4i32 (vsetcc (v4f32 VR128:$src1), VR128:$src2, cond: 
> $cc)),
> +          (CMPPSrri VR128:$src1, VR128:$src2, (SSE_CC_imm cond: 
> $cc))>;
> +def : Pat<(v4i32 (vsetcc (v4f32 VR128:$src1), (memop addr:$src2),  
> cond:$cc)),
> +          (CMPPSrmi VR128:$src1, addr:$src2, (SSE_CC_imm cond:$cc))>;
>
> // Shuffle and unpack instructions
> let Constraints = "$src1 = $dst" in {
> @@ -1675,13 +1696,17 @@
>                     (outs VR128:$dst), (ins VR128:$src1, VR128:$src,  
> SSECC:$cc),
>                     "cmp${cc}pd\t{$src, $dst|$dst, $src}",
>                     [(set VR128:$dst, (int_x86_sse2_cmp_pd  
> VR128:$src1,
> -                                       VR128:$src, imm:$cc))]>;
> +                                                        VR128:$src,  
> imm:$cc))]>;
>   def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
>                   (outs VR128:$dst), (ins VR128:$src1, f128mem:$src,  
> SSECC:$cc),
>                   "cmp${cc}pd\t{$src, $dst|$dst, $src}",
>                   [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
> -                                     (load addr:$src), imm:$cc))]>;
> +                                                  (load addr:$src),  
> imm:$cc))]>;
> }
> +def : Pat<(v2i64 (vsetcc (v2f64 VR128:$src1), VR128:$src2, cond: 
> $cc)),
> +          (CMPPDrri VR128:$src1, VR128:$src2, (SSE_CC_imm cond: 
> $cc))>;
> +def : Pat<(v2i64 (vsetcc (v2f64 VR128:$src1), (memop addr:$src2),  
> cond:$cc)),
> +          (CMPPDrmi VR128:$src1, addr:$src2, (SSE_CC_imm cond:$cc))>;
>
> // Shuffle and unpack instructions
> let Constraints = "$src1 = $dst" in {
>
>
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