[llvm-commits] [llvm] r50335 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

[Chris Lattner]

Author: lattner
Date: Mon Apr 28 01:02:19 2008
New Revision: 50335

URL: http://llvm.org/viewvc/llvm-project?rev=50335&view=rev
Log:
switch RegsForValue::Regs to be a SmallVector to avoid
heap thrash on tiny (usually single-element) vectors.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=50335&r1=50334&r2=50335&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Apr 28 01:02:19 2008
@@ -125,7 +125,7 @@
     /// Regs - This list holds the register (for legal and promoted values)
     /// or register set (for expanded values) that the value should be assigned
     /// to.
-    std::vector<unsigned> Regs;
+    SmallVector<unsigned, 4> Regs;
     
     /// RegVTs - The value types of the registers. This is the same size
     /// as ValueVTs; every register contributing to a given value must
@@ -146,11 +146,11 @@
                  unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
       : TLI(&tli), Regs(1, Reg), RegVTs(1, regvt), ValueVTs(1, valuevt) {}
     RegsForValue(const TargetLowering &tli,
-                 const std::vector<unsigned> &regs, 
+                 const SmallVectorImpl<unsigned> &regs, 
                  MVT::ValueType regvt, MVT::ValueType valuevt)
       : TLI(&tli), Regs(regs), RegVTs(1, regvt), ValueVTs(1, valuevt) {}
     RegsForValue(const TargetLowering &tli,
-                 const std::vector<unsigned> &regs, 
+                 const SmallVectorImpl<unsigned> &regs, 
                  const SmallVector<MVT::ValueType, 4> &regvts,
                  const SmallVector<MVT::ValueType, 4> &valuevts)
       : TLI(&tli), Regs(regs), RegVTs(regvts), ValueVTs(valuevts) {}
@@ -3600,7 +3600,7 @@
   
   
   MachineFunction &MF = DAG.getMachineFunction();
-  std::vector<unsigned> Regs;
+  SmallVector<unsigned, 8> Regs;
   
   // If this is a constraint for a single physreg, or a constraint for a
   // register class, find it.