[llvm-commits] [llvm] r50295 - /llvm/branches/Apple/Tak/lib/Target/X86/X86ISelLowering.cpp
Bill Wendling
isanbard at gmail.com
Fri Apr 25 13:23:14 PDT 2008
Author: void
Date: Fri Apr 25 15:23:14 2008
New Revision: 50295
URL: http://llvm.org/viewvc/llvm-project?rev=50295&view=rev
Log:
Merging r50292 into Tak.
Modified:
llvm/branches/Apple/Tak/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/branches/Apple/Tak/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Tak/lib/Target/X86/X86ISelLowering.cpp?rev=50295&r1=50294&r2=50295&view=diff
==============================================================================
--- llvm/branches/Apple/Tak/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/Apple/Tak/lib/Target/X86/X86ISelLowering.cpp Fri Apr 25 15:23:14 2008
@@ -1248,9 +1248,15 @@
ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
// Handle MMX values passed in GPRs.
- if (Is64Bit && RegVT != VA.getLocVT() && RC == X86::GR64RegisterClass &&
- MVT::getSizeInBits(RegVT) == 64)
- ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
+ if (Is64Bit && RegVT != VA.getLocVT()) {
+ if (MVT::getSizeInBits(RegVT) == 64 && RC == X86::GR64RegisterClass)
+ ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
+ else if (RC == X86::VR128RegisterClass) {
+ ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i64, ArgValue,
+ DAG.getConstant(0, MVT::i64));
+ ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
+ }
+ }
ArgValues.push_back(ArgValue);
} else {
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