[llvm-commits] [llvm] r49571 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/byval2.ll
Dan Gohman
gohman at apple.com
Fri Apr 11 19:35:39 PDT 2008
Author: djg
Date: Fri Apr 11 21:35:39 2008
New Revision: 49571
URL: http://llvm.org/viewvc/llvm-project?rev=49571&view=rev
Log:
Fix a bug that prevented x86-64 from using rep.movsq for
8-byte-aligned data.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/test/CodeGen/X86/byval2.ll
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=49571&r1=49570&r2=49571&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Apr 11 21:35:39 2008
@@ -4621,7 +4621,7 @@
ValReg = X86::EAX;
Val = (Val << 8) | Val;
Val = (Val << 16) | Val;
- if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) { // QWORD aligned
+ if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
AVT = MVT::i64;
ValReg = X86::RAX;
Val = (Val << 32) | Val;
@@ -4740,7 +4740,7 @@
break;
case 0: // DWORD aligned
AVT = MVT::i32;
- if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) // QWORD aligned
+ if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
AVT = MVT::i64;
break;
default: // Byte aligned
Modified: llvm/trunk/test/CodeGen/X86/byval2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/byval2.ll?rev=49571&r1=49570&r2=49571&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/byval2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/byval2.ll Fri Apr 11 21:35:39 2008
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep rep.movsl | count 2
+; RUN: llvm-as < %s | llc -march=x86-64 | grep rep.movsq | count 2
; RUN: llvm-as < %s | llc -march=x86 | grep rep.movsl | count 2
%struct.s = type { i64, i64, i64 }
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